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Texas Instruments TMS320C2810 Data Manual

Texas Instruments TMS320C2810 Data Manual

Digital signal processors
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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS174T
April 2001 – Revised May 2012

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Summary of Contents for Texas Instruments TMS320C2810

  • Page 1 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

  • Page 2: Table Of Contents

    ....................... OSC and PLL Block ..................... 3.8.1 Loss of Input Clock ....................PLL-Based Clock Module ................3.10 External Reference Oscillator Clock Option ......................3.11 Watchdog Block ....................3.12 Low-Power Modes Block ........................Peripherals Contents Copyright © 2001–2012, Texas Instruments Incorporated...
  • Page 3 6.24 External Interface Read Timing ..................6.25 External Interface Write Timing ........6.26 External Interface Ready-on-Read Timing With One External Wait State ........6.27 External Interface Ready-on-Write Timing With One External Wait State Contents Copyright © 2001–2012, Texas Instruments Incorporated...
  • Page 4 McBSP as SPI Master or Slave Timing ..................... 6.32 Flash Timing (F281x Only) ....................6.33 ROM Timing (C281x only) ..............6.34 Migrating From F281x Devices to C281x Devices ......................Revision History ......................Mechanical Data Contents Copyright © 2001–2012, Texas Instruments Incorporated...
  • Page 5 List of Figures ......TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View) ............. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) ....TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View) ....................... Functional Block Diagram ..................... F2812/C2812 Memory Map .....................
  • Page 6 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ........... 6-47 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ........... 6-48 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 List of Figures Copyright © 2001–2012, Texas Instruments Incorporated...
  • Page 7 XCLKIN Timing Requirements – PLL Disabled ................... Possible PLL Configuration Modes ............6-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ..................6-11 Reset (XRS) Timing Requirements ................... 6-12 IDLE Mode Timing Requirements List of Tables Copyright © 2001–2012, Texas Instruments Incorporated...
  • Page 8 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ......6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ............... 6-60 Flash Endurance for A and S Temperature Material List of Tables Copyright © 2001–2012, Texas Instruments Incorporated...

  • Page 9: List Of Tables

    Minimum Required ROM Wait States at Different Frequencies (C281x devices) ..............Thermal Resistance Characteristics for 179-Ball GHH ..............Thermal Resistance Characteristics for 179-Ball ZHH ..............Thermal Resistance Characteristics for 176-Pin PGF ..............Thermal Resistance Characteristics for 128-Pin PBK List of Tables Copyright © 2001–2012, Texas Instruments Incorporated...

  • Page 10: Tms320F281X, Tms320C281X Dsps

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar BGA, TMS320C28x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TI, TMS320C54x, TMS320C55x, TMS320 are trademarks of Texas Instruments.

  • Page 11: Getting Started

    Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0) • C2000 Getting Started Website (http://www.ti.com/c2000getstarted) • TMS320F28x DSC Development and Experimenter’s Kits (http://www.ti.com/f28xkits) TMS320F281x, TMS320C281x DSPs Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 12: Introduction

    3, Functional Overview. Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811, and TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices.

  • Page 13: Device Summary

    (1) The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed. (2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module.

  • Page 14: Pin Assignments

    XD[15] XA[14] XA[11] ADCINA0 ADCINA4 SCIRXDA TESTSEL SSAIO DDA2 XPLLDIS Figure 2-1. TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View) Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 15: Pin Assignments For The Pgf Package

    PWM12 ADCINA2 PWM11 ADCINA1 PWM10 ADCINA0 PWM9 ADCLO PWM8 PWM7 SSAIO Figure 2-2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 16: Pin Assignments For The Pbk Package

    TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com 2.3.3 Pin Assignments for the PBK Package The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-3. See Table 2-2 for a description of each pin’s...

  • Page 17: Signal Descriptions

    (3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3, Electrical Characteristics Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode. Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 18 XREADY – XREADY can be configured to be a synchronous or an asynchronous input. See the timing diagrams for more details. Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 19 “no connect (NC)” (that is, this pin is not connected to any circuitry internal to the device). Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 20 Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 21 NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system. Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 22 Core and Digital I/O Ground Pins – – – – – – – – – – – – – – – – – – – – Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 23 GPIO or Capture Input #6 GPIOB11 - TDIRB (I) GPIO or Timer Direction GPIOB12 - TCLKINB (I) GPIO or Timer Clock Input Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 24 GPIOF12 - MDXA (O) – GPIO or McBSP transmitted serial data GPIOF13 - MDRA (I) GPIO or McBSP received serial data Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 25 Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with the 3.3-V supply. Introduction Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 26: Functional Overview

    On C281x devices, the OTP is replaced with a 1K x 16 block of ROM. Figure 3-1. Functional Block Diagram Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 27: Memory Map

    Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations. Figure 3-2. F2812/C2812 Memory Map Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 28: F2812/C2812 Memory Map

    “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order. Certain memory ranges are EALLOW protected against spurious writes after configuration. Figure 3-3. F2811/C2811 Memory Map Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 29: F2811/C2811 Memory Map

    “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order. Certain memory ranges are EALLOW protected against spurious writes after configuration. Figure 3-4. F2810/C2810 Memory Map Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 30: Addresses Of Flash Sectors In F2812 And F2811

    24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7 (if MP/MC mode is high). Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 31: Wait States

    Programmed via the XINTF registers. Programmable, XINTF Cycles can be extended by external memory or peripheral. 1-wait minimum 0-wait operation is not possible. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 32: Brief Descriptions

    Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) 3.2.3 Peripheral Bus To enable migration of peripherals between various Texas Instruments ( TI™) DSP family of devices, the F281x and C281x adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor “Memory Bus”...

  • Page 33: Real-Time Jtag And Analysis

    1K x 16 ROM block that replaces the OTP memory available in flash devices. For information on how to submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide (literature number SPRU430). Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 34: M0, M1 Sarams

    To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which matches the value stored in the password locations within the Flash/ROM. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 35: Impact Of Using The Code Security Module

    Application code and data 0x3F 7FF0 – 0x3F 7FF5 0x3D 7BFC – 0x3D 7BFF Application code and data (1) See the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature number SPRZ193) for some restrictions. Disclaimer Code Security Module Disclaimer...

  • Page 36: Peripheral Interrupt Expansion (Pie) Block

    Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible power consumption mode. Only a reset or XNMI can wake the device from this mode. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 37: Peripheral Frames 0, 1, 2 (Pfn)

    ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample- and-hold units for simultaneous sampling. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 38: Serial Port Peripherals

    UART. On the F281x and C281x, the port supports a 16-level, receive-and- transmit FIFO for reducing servicing overhead. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 39: Register Map

    3584 (1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 40: Peripheral Frame 2 Registers

    (1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written). Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 41: Device Emulation Registers

    0x00 0884 Block Protection Start Address Register PROTRANGE 0x00 0885 Block Protection Range Address Register Reserved 0x00 0886 – 0x00 09FF Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 42: External Interface, Xintf (2812 Only)

    Zone 7 is disabled (via the MP/MC mode), then any external memory is still accessible via Zone 6 address space. XCLKOUT is also pinned out on the 2810 and 2811. Figure 3-5. External Interface Block Diagram Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 43: Timing Registers

    BIT(S) NAME TYPE RESET DESCRIPTION Current XINTF Revision. For internal use/reference. Test purposes 15–0 REVISION 0x0004 only. Subject to change. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 44: Interrupts

    PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 45: Multiplexing Of Interrupts Using The Pie Block

    No peripheral within the group is asserting interrupts. • No peripheral interrupts are assigned to the group (example PIE group 12). Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 46: Pie Configuration And Control Registers

    Reserved (1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 47: External Interrupts

    Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078). Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 48: System Control

    CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency. Figure 3-8. Clock and Reset Domains Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 49: Pll, Clocking, Watchdog, And Low-Power Mode Registers

    (2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not reset PLLCR. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 50: Osc And Pll Block

    X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed V . The PLLCR bits [3:0] set the clocking ratio. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 51: Loss Of Input Clock

    Such a circuit would also help in detecting failure of the V rail. DD3VFL Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 52: Pll-Based Clock Module

    (load capacitance) = 12 pF • = 24 pF • = 6 pF shunt • ESR range = 25 to 40 Ω Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 53: Watchdog Block

    In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so is the WATCHDOG. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 54: Low-Power Modes Block

    The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them when the IDLE instruction was executed. Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 55: Peripherals

    32-Bit Timer Period TDDRH:TDDR PRDH:PRD 16-Bit Prescale Counter SYSCLKOUT PSCH:PSC TCR.4 32-Bit Counter (Timer Start Status) Borrow TIMH:TIM Borrow TINT Figure 4-1. CPU-Timers Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 56: Cpu-Timer Interrupts Signals And Output Signal

    For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078). Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 57: Cpu-Timers 0, 1, 2 Configuration And Control Registers

    TIMER2TPR 0x00 0C16 CPU-Timer 2, Prescale Register TIMER2TPRH 0x00 0C17 CPU-Timer 2, Prescale Register High Reserved 0x00 0C18 – 0x00 0C3F Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 58: Event Manager Modules (Eva, Evb)

    External Trip Inputs T2CTRIP/EVASOC T4CTRIP/EVBSOC (1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 59: Eva Registers

    (1) The EV-B register set is identical except the address range is from 0x00 7500 to 0x00 753F. The above registers are mapped to Zone 2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results. (2) New register compared to 24x/240x Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 60 Index Qual CAPCONA[15:12,7:0] EXTCONA[1:2] The EVB module is similar to the EVA module. Figure 4-3. Event Manager A Functional Block Diagram Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 61: General-Purpose (Gp) Timers

    (beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for compare value reload. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 62: Pwm Characteristics

    EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 63: Enhanced Analog-To-Digital Converter (Adc) Module

    Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 64: Block Diagram Of The F281X And C281X Adc Module

    If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 65: Adc Pin Connections With Internal Reference

    Figure 4-5. ADC Pin Connections With Internal Reference NOTE The temperature rating of any recommended component must match the rating of the end product. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 66: Adc Pin Connections With External Reference

    TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more information. Figure 4-6. ADC Pin Connections With External Reference Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 67: Adc Registers

    ADCST 0x00 7119 ADC Status Register Reserved 0x00 711C – 0x00 711F (1) The above registers are Peripheral Frame 2 Registers. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 68: Enhanced Controller Area Network (Ecan) Module

    NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps. The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for details. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 69: Ecan Block Diagram And Interface Circuit

    Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.3-V CAN Transceiver CAN Bus Figure 4-7. eCAN Block Diagram and Interface Circuit Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 70: V Ecan Transceivers For The Tms320F281X And Tms320C281X Dsps

    –40°C to 125°C Built-in Isolation Low Prop Delay ISO1050 3–5.5 V None None None Thermal Shutdown –55°C to 105°C Failsafe Operation Dominant Time-out Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 71: Ecan Memory Map

    If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 72: Can Registers

    Time-out control (Reserved in SCC mode) CANTOS 0x00 6032 Time-out status (Reserved in SCC mode) (1) These registers are mapped to Peripheral Frame 1. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 73: Multichannel Buffered Serial Port (Mcbsp) Module

    (2) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 74: Mcbsp Module With Fifo

    Interrupt To CPU RX FIFO _0 RX FIFO _0 RX FIFO Registers Peripheral Read Bus Figure 4-9. McBSP Module With FIFO Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 75: Mcbsp Registers

    McBSP Transmit Channel Enable Register Partition H (1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 76 MFFST 0x0000 McBSP FIFO Status Register (2) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 77: Serial Communications Interface (Sci) Module

    (3) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 78: Sci-A Registers

    (1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 79: Serial Communications Interface (Sci) Module Block Diagram

    RX Error RX ERR INT ENA SCI RX Interrupt Select Logic SCICTL1.6 Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 80: Serial Peripheral Interface (Spi) Module

    (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • 16-level transmit/receive FIFO • Delayed transmit control Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 81: Spi Registers

    SPI Priority Control Register (1) These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 82: Serial Peripheral Interface Module Block Diagram (Slave Mode)

    SPISTE is driven low by the master for a slave device. Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode) Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 83: Gpio Mux

    (2) Not all inputs support input signal qualification. (3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 84: Gpio Data Registers

    (1) Reserved locations will return undefined values and writes will be ignored. (2) These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 85: Gpio/Peripheral Pin Multiplexing

    PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1. Peripherals Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 86: Development Support

    Development Support Texas Instruments ( TI™) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

  • Page 87: Documentation Support

    These device-specific differences are listed in the peripheral reference guides. Development Support Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 88 (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is used for communications between the DSP controller and external peripherals or another controller. Development Support Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 89: Community Resources

    Updated information on the TMS320™ DSP controllers can be found on the worldwide web at: http://www.ti.com. To send comments regarding this TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811,TMS320C2812 Digital Signal Processors Data Manual (literature number SPRS174), click on the Submit Documentation Feedback link at the bottom of the page. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm...
  • Page 90 TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Development Support Copyright ©...

  • Page 91: Electrical Specifications

    DDAIO DDA1 DDA2 DD3VFL (2) Group 2 pins are as follows: XINTF pins, T1CTRIP_PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 92: Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)

    (3) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5. (4) The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 93: Current Consumption

    ). It includes a small amount of current (<1 mA) drawn by V NOTE HALT and STANDBY modes cannot be used when the PLL is disabled. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 94: Tms320C281X Current Consumption By Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes At 150-Mhz Sysclkout

    1.8-V rail (V ). It includes a small amount of current (<1 mA) drawn by V Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 95: Current Consumption Graphs

    Figure 6-1. F2812/F2811/F2810 Typical Current Consumption Over Frequency SYSCLKOUT (MHz) Total Power Figure 6-2. F2812/F2811/F2810 Typical Power Consumption Over Frequency Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 96: F2812/F2811/F2810 Typical Power Consumption Over Frequency

    Figure 6-3. C2812/C2811/C2810 Typical Current Consumption Over Frequency SYSCLKOUT (MHz) Total Power Figure 6-4. C2812/C2811/C2810 Typical Power Consumption Over Frequency Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 97: Reducing Current Consumption

    DDIO EMU0 EMU0 EMU1 EMU1 TRST TRST TCK_RET JTAG Header Figure 6-5. Emulator Connection Without Signal Buffering for the DSP Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 98: Power Sequencing Requirements

    C2000 (3 Voltage Rail Monitors) NOTE The GPIO pins are undefined until V = 1 V and V = 2.5 V. DDIO Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 99: F2812/F2811/F2810 Typical Power-Up And Power-Down Sequence - Option 2

    Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up. Figure 6-6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 100: Signal Transition Levels

    V and higher. IL(MAX) IH(MIN) NOTE See the individual timing diagrams for levels used for testing timing parameters. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 101: Timing Parameter Symbology

    Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6-9. 3.3-V Test Load Circuit Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 102: Device Clock Table

    (2) The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 103: Clock Requirements And Characteristics

    (XCLKIN * n) / 2 PLL block now divides the output of the PLL by two before feeding it to the CPU. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 104: Output Clock Characteristics

    TMS320x281x DSP Boot ROM Reference Guide (literature number SPRU095) and the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078) for further information. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 105 1 V and 3.3-V supply reaches 2.5 V. Figure 6-11. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 106: Power-On Reset In Microcomputer Mode (Xmp/Mc = 0) (See Note D)

    1 V and 3.3-V supply reaches 2.5 V. Figure 6-12. Power-on Reset in Microprocessor Mode (XMP/MC = 1) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 107: Power-On Reset In Microprocessor Mode (Xmp/Mc = 1)

    This Period (PLL Lock-up Time, t ) is 131 072 XCLKIN Cycles Long.] Figure 6-14. Effect of Writing Into PLLCR Register Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 108: Low-Power Mode Wakeup Timing

    XCLKOUT = SYSCLKOUT WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. Figure 6-15. IDLE Entry and Exit Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 109: Standby Mode Timing Requirements

    (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up) signal involves additional latency. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 110: Standby Entry And Exit Timing

    After a latency period, the STANDBY mode is exited. Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-16. STANDBY Entry and Exit Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 111: Halt Wakeup Using Xnmi

    When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. Normal operation resumes. XCLKOUT = SYSCLKOUT Figure 6-17. HALT Wakeup Using XNMI Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 112: Event Manager Interface

    PWMx XCLKOUT = SYSCLKOUT Figure 6-18. PWM Output Timing XCLKOUT w(TDIR) TDIRx XCLKOUT = SYSCLKOUT Figure 6-19. TDIRx Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 113: Tdirx Timing

    Pulse duration, EVBSOC low w(EVBSOCL) c(HCO) (1) XCLKOUT = SYSCLKOUT XCLKOUT d(XCOH-EVBSOCL) w(EVBSOCL) EVBSOC Figure 6-21. EVBSOC Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 114: Interrupt Timing

    CxTRIP pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit. Figure 6-22. External Interrupt Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 115: General-Purpose Input/Output (Gpio) - Output Timing

    All GPIOs f(GPO) Toggling frequency, GPO pins XCLKOUT d(XCOH-GPO) GPIO r(GPO) f(GPO) XCLKOUT = SYSCLKOUT Figure 6-23. General-Purpose Output Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 116: General-Purpose Input/Output (Gpio) - Input Timing

    Since external signals are driven asynchronously, a 13-SYSCLKOUT-wide pulse provides reliable recognition. Figure 6-24. GPIO Input Qualifier – Example Diagram for QUALPRD = 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 117: Serial Peripheral Interface (Spi) Master Mode Timing

    (clock phase = 0) and Table 6-27 lists the timing (clock phase = 1). Figure 6-26 Figure 6-27 show the timing waveforms. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 118: Spi Master Mode External Timing (Clock Phase = 0)

    Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX. • Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 119: Spi Master Mode External Timing (Clock Phase = 0)

    (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-26. SPI Master Mode External Timing (Clock Phase = 0) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 120: Spi Master Mode External Timing (Clock Phase = 1)

    Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX. • Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 121: Spi Master External Timing (Clock Phase = 1)

    FIFO and non-FIFO modes. Figure 6-27. SPI Master External Timing (Clock Phase = 1) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 122: Serial Peripheral Interface (Spi) Slave Mode Timing

    Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX. • Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 123: Spi Slave Mode External Timing (Clock Phase = 0)

    (SPICLK) of the last data bit. c(SPC) Figure 6-28. SPI Slave Mode External Timing (Clock Phase = 0) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 124: Spi Slave Mode External Timing (Clock Phase = 1)

    Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX. • Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 125: Spi Slave Mode External Timing (Clock Phase = 1)

    (SPICLK) of the last data bit. c(SPC) Figure 6-29. SPI Slave Mode External Timing (Clock Phase = 1) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 126: External Interface (Xintf) Timing

    Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0, 1 Valid 0, 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 127 Examples of valid and invalid timing when using synchronous XREADY (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0, 1 Invalid 0, 1 Valid 0, 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 128 XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0, 1 Invalid 0, 1 Invalid Valid Valid 0, 1 Valid 0, 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 129: Relationship Between Xtimclk And Sysclkout

    C28x XCLKOUT XTIMCLK XINTCNF2 XINTCNF2 (CLKOFF) (XTIMCLK) XINTCNF2 (CLKMODE) Default value after reset Figure 6-30. Relationship Between XTIMCLK and SYSCLKOUT Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 130: Xintf Signal Alignment To Xclkout

    + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of XCLKOUT. Examples: XZCSH Zone chip-select inactive-high XRNWH XR/W inactive-high Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 131: External Interface Read Timing

    Hold time, read data valid after XRD inactive-high h(XD)XRD (1) LR = Lead period, read access. AR = Active period, read access. See Table 6-30. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 132: Example Read Access

    USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE ≥ 1 ≥ 0 ≥ 0 (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 133: External Interface Write Timing

    USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE ≥ 1 ≥ 0 ≥ 0 (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 134: External Interface Ready-On-Read Timing With One External Wait State

    D = (XRDLEAD + XRDACTIVE – 3 + n) t – t c(XTIM) su(XRDYAsynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth). Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 135: Example Read With Synchronous Xready Access

    XWRLEAD XWRACTIVE XWRTRAIL READYMODE 0 = XREADY ≥ 1 ≥ 1 (Synch) (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 136: Example Read With Asynchronous Xready Access

    XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 = XREADY ≥ 1 ≥ 1 (Async) (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 137: External Interface Ready-On-Write Timing With One External Wait State

    D = (XWRLEAD + XWRACTIVE – 3 + n) t – t c(XTIM) su(XRDYasynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth). Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 138: Write With Synchronous Xready Access

    XWRLEAD XWRACTIVE XWRTRAIL READYMODE 0 = XREADY ≥ 1 ≥ 1 (Synch) (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 139: Write With Asynchronous Xready Access

    XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 = XREADY ≥ 1 ≥ 1 (Async) (1) N/A = “Don’t care” for this example Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 140: Xhold And Xholda

    All other signals not listed in this group remain in their default or functional operational modes during these signal events. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 141: Xhold/Xholda Timing

    See Note (A) See Note (B) All pending XINTF accesses are completed. Normal XINTF operation resumes. Figure 6-37. External Interface Hold Waveform Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 142: Xhold/Xholda Timing Requirements (Xclkout = 1/2 Xtimclk)

    See Note (A) All pending XINTF accesses are completed. Normal XINTF operation resumes. Figure 6-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 143: On-Chip Analog-To-Digital Converter

    (1) The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V or below V . The continuous clamp current per pin is ±2 mA. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 144: Adc Electrical Characteristics Over Recommended Operating Conditions

    – 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin. To avoid this, the analog inputs should be kept within these limits. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 145: Current Consumption For Different Adc Configurations

    Sampling Capacitor (C ): 1.25 pF Parasitic Capacitance (C ): 10 pF Source Resistance (R ): 50 Figure 6-39. ADC Analog Input Impedance Model Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 146: Adc Power-Up Control Bit Timing

    The conversion can be performed in two different conversion modes: • Sequential sampling mode (SMODE = 0) • Simultaneous sampling mode (SMODE = 1) Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 147: Sequential Sampling Mode (Single-Channel) (Smode = 0)

    Delay time for successive results to (2 + Acqps) * t 80 ns d(schx_n+1) c(ADCCLK) appear in the Result register Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 148: Simultaneous Sampling Mode (Dual-Channel) (Smode = 1)

    Delay time for successive results to (3 + Acqps) * t 120 ns d(schB0_n+1) c(ADCCLK) appear in Result register Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 149: Definitions Of Specifications And Terminology

    Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 150: Multichannel Buffered Serial Port (Mcbsp) Timing

    (3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (20 MHz). Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 151: Mcbsp Switching Characteristics

    (2) 2P = 1/CLKG in ns. (3) C = CLKRX low pulse width = P D = CLKRX high pulse width = P Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 152: Mcbsp Receive Timing

    Bit 0 (XDATDLY=00b) Bit (n-1) (n-2) (n-3) Bit 0 (XDATDLY=01b) Bit (n-1) (n-2) Bit 0 (XDATDLY=10b) Figure 6-44. McBSP Transmit Timing Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 153: Mcbsp As Spi Master Or Slave Timing

    (n-2) (n-3) (n-4) Bit 0 Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 154: Mcbsp Timing As Spi Master Or Slave: Clkstp = 11B, Clkxp

    Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 155: Mcbsp Timing As Spi Master Or Slave: Clkstp = 10B, Clkxp = 1

    (n-2) (n-3) (n-4) Bit 0 Figure 6-47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 156: Mcbsp Timing As Spi Master Or Slave: Clkstp = 11B, Clkxp = 1

    (n-2) (n-3) (n-4) Bit 0 Figure 6-48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 157: Flash Timing (F281X Only)

    However, the erase operation is needed on all subsequent programming operations. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 158: Flash/Otp Access Timing

    ÷ ê ú c(SCO) è ø ë û (2) Random wait state must be greater than or equal to 1. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 159: Rom Access Timing

    ÷ ê ú c(SCO) è ø ë û (2) Random wait state must be greater than or equal to 1. Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 160: Migrating From F281X Devices To C281X Devices

    • The PART-ID register value is different for Flash and ROM parts. For errata applicable to 281x devices, see the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature number SPRZ193). Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated...

  • Page 161: Revision History

    Flash Parameters at 150-MHz SYSCLKOUT: • Added footnote about flash memory being in an erased state when the device is shipped Revision History Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...

  • Page 162: Mechanical Data

    Θ 10.76 °C/W The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). Mechanical Data Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812...
  • Page 163 PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS320C2810PBKA ACTIVE LQFP Call TI Call TI -40 to 85 TMS320C2810PBKQ ACTIVE LQFP...
  • Page 164 PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2014 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS320F2812PGFQ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 320F2812PGFQ &...
  • Page 165 PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
  • Page 171 MECHANICAL DATA OCTOBER 1994 PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 0,27 0,08 0,17 0,50 0,13 NOM Gage Plane 21,50 SQ 24,20 23,80 0,25 0,05 MIN 26,20 0°−7° 25,80 0,75 1,45 0,45 1,35 Seating Plane 0,08 1,60 MAX 4040134 / B 03/95 NOTES: A.
  • Page 172 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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