Register Bits Used To Set The Receive Interrupt Mode - Texas Instruments TMS320VC5501 Reference Manual

Setting the Receive Interrupt Mode
7.15 Setting the Receive Interrupt Mode
Figure 7−15. Register Bits Used to Set the Receive Interrupt Mode
SPCR1
15
Legend: R = Read; W = Write; -n = Value after reset
Table 7−18. Register Bits Used to Set the Receive Interrupt Mode
Register Bit Name
SPCR1 5–4 RINTM
7.15.1 About the Receive Interrupt and the Associated Modes
7-22 Receiver Configuration
The RINTM bits (see Figure 7−15 and Table 7−18) determine which event
generates a receive interrupt request to the CPU.
Function
Receive Interrupt Mode
RINTM = 00
RINTM = 01
RINTM = 10
RINTM = 11
The receive interrupt (RINT) signals the CPU of changes to the serial port
status. Four options exist for configuring this interrupt. The options are set by
the receive interrupt mode bits, RINTM, in SPCR1.
RINTM = 00b. Interrupt on every serial word by tracking the RRDY bit in
-
SPCR1. Note that regardless of the value of RINTM, RRDY can be read
to detect the RRDY = 1 condition.
RINTM = 01b. In the multichannel selection mode, interrupt after every
-
16-channel block boundary has been crossed within a frame and at the
end of the frame. In any other serial transfer case, this setting is not
applicable and, therefore, no interrupts are generated.
RINTM = 10b. Interrupt on detection of receive frame-sync pulses. This
-
generates an interrupt even when the receiver is in its reset state. This is
done by synchronizing the incoming frame-sync pulse to the McBSP
internal input clock and sending it to the CPU via RINT.
RINTM = 11b. Interrupt on frame-synchronization error. Note that
-
regardless of the value of RINTM, RSYNCERR can be read to detect this
condition.
6 5
RINTM
R/W-00
RINT generated when RRDY changes from 0 to 1
RINT generated by an end-of-block or end-of-frame
condition in the receive multichannel selection mode
RINT generated by a new receive frame-sync pulse
RINT generated when RSYNCERR is set
4 3
SPRU592E
0