Inter-Dsp Interrupt Registers (Ipcgr0-Ipcgr2 And Ipcar0-Ipcar2) - Texas Instruments TMS320C6474 Manual

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3.5

Inter-DSP Interrupt Registers (IPCGR0-IPCGR2 and IPCAR0-IPCAR2)

The IPCGRn (IPCGR0 thru IPCGR2) and IPCARn (IPCAR0 thru IPCAR2) registers facilitate inter-DSP
interrupts. This can be utilized by external hosts or C64x+ megamodules to generate interrupts to other
DSPs. A write of 1 to the IPCG field of IPCGRn register generates an interrupt pulse to C64x+
Megamodulen (n = 0-2). These registers also provide a source ID, by which up to 28 different sources of
interrupts can be identified.
31 30 29 28
SRCS27 SRCS26 SRCS25 SRCS24
R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12
SRCS11 SRCS10 SRCS9 SRCS8
R/W- R/W-0 R/W-0 R/W-0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-5. IPC Generation Registers (IPCGR0-IPCGR2) Field Descriptions
Bit Field
31:4 SRCS[27:0]
3:1 Reserved
0 IPCG
Copyright © 2008–2010, Texas Instruments Incorporated
27 26 25
SRCS23 SRCS22 SRCS21 SRCS20
R/W-0 R/W-0 R/W-0 R/W-0
11 10 9
SRCS7 SRCS6 SRCS5
R/W-0 R/W-0 R/W-0 R/W-0
Figure 3-3. IPC Generation Registers (IPCGR0-IPCGR2)
Value Description
Write:
0 No effect
1 Set register bit
Read:
Returns current value of internal register bit
Reserved
Write:
0 No effect
1 Create an inter-DSP interrupt pulse to the corresponding C64x+ megamodule (C64x+
Megamodule0 for IPCGR0, etc.)
Read:
Returns 0, no effect
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24 23 22 21
SRCS19 SRCS18 SRCS17
R/W-0 R/W-0 R/W-0
8 7 6 5
SRCS4 SRCS3 SRCS2 SRCS1
R/W-0 R/W-0 R/W-0
:TMS320C6474
TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
20 19 18
SRCS16 SRCS15 SRCS14 SRCS13
R/W-0 R/W-0 R/W-0 R/W-0
4 3
SRCS0 Reserved
R/W-0 R-000
Device Configuration
17 16
SRCS12
R/W-0
1 0
IPCG
R/W-0
49