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7.9 Interrupts
7.9.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6670 device are configured through the C66x CorePac Interrupt Controller. The
Interrupt Controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of 25 internally-generated events (within the CorePac) and 103 chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In addition, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through Chip Interrupt Controller (CIC) blocks, CIC[2:0] for C6670 device.
This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, plus
the EDMA3CC. CIC0 provides 26 additional events (18 that are CorePac-specific plus 8 broadcast) to each of the
C66x CorePacs, CIC1 provides 19 and 21 additional events to CC1 and CC2, respectively, and CIC2 provides 10 and
32 additional events to CC0 and HyperLink, respectively.
The events that are routed to the C66x CorePacs for AET purposes, from those EDMA3CC and FSYNC events that
are not otherwise provided to each C66x CorePac. For more details on the CIC features, please see the Chip Interrupt
Controller (CIC) for KeyStone Devices User Guide in
page
66.
Modules such as FFTC, TCP3d, TCP3e, TAC, AIF, CP_MPU, BOOT_CFG, and Tracer have level
Note—
interrupts and EOI handshaking interface. The EOI value is 0 for TCP3d, TCP3e, TAC, AIF, CP_MPU,
BOOT_CFG, and Tracer. For FFTC, the EOI values are 0 for FFTC_x_INTD0, 1 for FFTC_x_INTD01, 2
for FFTC_x_INTD2, and 3 for FFTC_x_INTD3 (where FFTC_x can be either FFTC_0 or FFTC_1).
Copyright 2012 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point System-on-Chip
2.9 ''Related Documentation from Texas Instruments'' on
TMS320C6670 Peripheral Information and Electrical Specifications
TMS320C6670
SPRS689D—March 2012
155
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