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31
0
0
0
15
0
0
0
5-30
If this bit is set to '1' and the corresponding mask bit in
the
INTA/ interrupt will be generated.
R
Reserved
Reserved for future use.
DI
Doorbell Interrupt (Read Only)
This bit is the System Doorbell Interrupt. It is set to '1'
when the IOP writes a value to the System Doorbell. It is
cleared by a write of any value to this register. If this bit
is set to '1' and the corresponding mask bit in the
Host Interrupt Mask Register
interrupt will be generated.
Register: 0x034
Host Interrupt Mask Register
Read/Write
0
0
0
0
R
0
0
0
0
The
Host Interrupt Mask Register
reported in the
Host Interrupt Status
R
Reserved
Reserved for future use.
RIM
Reply Interrupt Mask (Read/Write)
This bit when set to '1' masks the Reply Interrupt
condition (prevents the assertion of PCI INTA/).
R
Reserved
Reserved for future use.
DIM
Doorbell Interrupt Mask (Read/Write)
This bit when set to '1' masks the System Doorbell
Interrupt condition (prevents the assertion of PCI INTA/).
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Host Interrupt Mask Register
R
0
0
0
0
0
0
is used to mask the interrupt conditions
Register.
is cleared to '0', a PCI
is cleared to '0', a PCI INTA/
0
0
0
0
4
3
2
RIM
0
0
1
0
[2:1]
0
16
0
0
1
0
R
DIM
0
1
[31:4]
3
[2:1]
0
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