Table of Contents
Advertisement
Table 4.3
Memory Interface (Cont.)
Signal
I/O
MCLK
O
ADSC/
O
ADV/
O
BWE[3:0]/
O
RAMCS/
O
ZZ
O
BGA Pad
Number
Pad Type Description
A23
3.3 V
8 mA T/S
Output
C22
3.3 V
4 mA T/S
Output
B22
3.3 V
4 mA T/S
Output
B21, A22, C20,
3.3 V
A21
BiDir
4 mA
C19
3.3 V
BiDir
4 mA
D19
3.3 V
BiDir
4 mA
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Memory Clock. All synchronous RAM
control/data signals are referenced to the rising
edge of this clock. Exceptions are MOE/ and
ZZ which are typically asynchronous inputs to
SRAM and/or FLASH devices.
Address-Strobe-Controller. Initiates READ,
WRITE, or chip deselect cycle. When this
signal is asserted, it also latches the memory
address signals.
Advance. When asserted LOW, the ADV/ input
causes a selected synchronous SRAM to
increment its burst address counter.
Memory Byte Write Enables. These
active-LOW, byte lane write enables allow
writing of partial words to memory.
RAM Chip Select. This pin is an active-LOW
synchronous chip select for all SSRAMS (up to
four SSRAMS for interleaved and depth
expanded configuration without additional
decode logic).
Snooze Control. Asserting this output HIGH
will cause a synchronous SRAM to enter its
lowest power state (not all RAMs support this
function).
4-11
Advertisement
Table of Contents
