Pci Cache Mode; Pci Bus Commands And Encoding Types - LSI LSIFC929 Technical Manual

Table 5.1

PCI Bus Commands and Encoding Types

C_BE[3:0]/ Command Type
0000 Special Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read Cycle
0011 I/O Write Cycle
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Dual Address Cycle
1110 Memory Read Line
1111 Memory Write and Invalidate

5.3 PCI Cache Mode

The LSIFC929 supports the PCI specification for an 8-bit
Size register located in PCI configuration space. The
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. Memory Write and Invalidate is
enabled using bit 4 of the
Cache Read commands cannot be disabled. Slaves, however, can alias
the Memory Read Line and Memory Read Multiple commands to the
Memory Read command.
PCI Cache Mode
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Supported as Master
No
No
Yes
Yes
N/A
N/A
Yes
Yes
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Command Register in PCI configuration space.
Supported as Slave
No
No
Yes
Yes
N/A
N/A
Yes
Yes
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Cache Line
Cache Line Size
5-3