Support For Pci Cache Line Size Register; Selection Of Cache Line Size; Memory Write And Invalidate Command - LSI LSIFC929 Technical Manual

5.3.1 Support for PCI Cache Line Size Register

5.3.2 Selection of Cache Line Size

5.3.3 Memory Write and Invalidate Command

5.3.3.1 Alignment
5-4
The LSIFC929 supports the PCI specification for an 8-bit
Size register in PCI configuration space; it can sense and react to
nonaligned addresses corresponding to cache line boundaries.
The cache logic selects a cache line size based on the value specified
in the Cache Line Size
Note: If a value of 1 is specified in the PCI Cache Line size
register, caching is disabled. Otherwise, the LSIFC929
uses whatever legal value is specified (2, 4, 8, 16, 32, 64,
or 128) for all aligned burst data transfers.
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; i.e., the master intends to write all
bytes within the addressed cache line in a single PCI transaction, unless
interrupted by the target. This command requires implementation of the
PCI Cache Line Size register at address 0x00C in the PCI configuration
space.
The LSIFC929 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a noncache
command.
For nonaligned initial addresses, the chip executes a burst to bring the
address counter to an aligned value. Once a cache line boundary is
reached, the chip uses the cache line size as the burst size from then
on, except in the case of
process is finished at this point. Memory Write and Invalidate commands
are issued when the following conditions are met:
Registers
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register.
Multiple Cache Line
Cache Line
Transfers. The alignment