Bit Dual-Address Cycle - LSI LSIFC929 Technical Manual

Figure 6.10 64-Bit Dual-Address Cycle
(Driven by System)
REQ64/
(Driven by LSIFC929)
FRAME/
(Driven by LSIFC929)
AD[31:0]
(Driven by LSIFC929 - Address;
Target - Data)
AD[63:32]
(Driven by Target)
C_BE[3:0]/
(Driven by LSIFC929)
C_BE [7:4]/
(Driven by LSIFC929)
(Driven by LSIFC929 - Address;
Target - Data)
(Driven by LSIFC929)
(Driven by Target)
(Driven by Target)
DEVSEL/
(Driven by Target)
ACK64/
(Driven by Target)
6-16
CLK
PAR
IRDY/
TRDY/
STOP/
Specifications
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
t
3
t
3
t
3
Low High
Address Address
High Address
t
3
Dual Bus
Address CMD
t
3
Bus CMD
t
3
Address
Parity
t
3
t
1
t
1
t
1
t
1
Data
In
t
2
t
1
Data
In
t
2
Byte Enable
Byte Enable
t
1
Data
Parity
t
2
t
2
t
2
t
2