Table of Contents
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Numerics
4 mA bidirectional signals
6-3
64EN/
4-7
8 mA output signals
6-3
8b/10b decoding
2-2
8b/10b encoding
2-2
A
AC timing
6-6
ACK64/
4-3
AD[63:0]
4-4
ADSC/
4-11
ADV/
4-11
arbitrated loop topology
2-8
architecture
1-6
ARMEN/
4-12
B
BER
1-9
BGA position
6-24
BIST
5-13
bit error rate
1-9
block diagram
3-2
BWE[3:0]/
4-11
BYPASS0/
4-9
BYPASS1/
4-9
C
C_BE[7:0]/
4-4
Cache Line Size
5-13
Capabilities Pointer
5-20
capacitance
6-2
channel protocol
2-1
class 1
2-9
class 2
2-9
class 3
2-9
Class Code
5-13
class intermix
2-10
classes of service
2-9
Command
5-10
Command Descriptor Block (CDB)
configuration registers. See PCI configuration registers
context manager
1-9
controller
link
1-8
memory
1-7
CRC
2-4
Index
2-6
LSIFC929 Dual Channel Fibre Channel I/O Processor
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Cyclic Redundancy Check (CRC)
D
data flows
3-2
data frames 2-3,
2-4
data sequence
2-6
decoding 8b/10b
2-2
destination identifier (D_ID)
Device ID
5-9
DEVSEL/
4-5
dual address cycle (DAC)
1-7
E
encode/decode
2-2
End-of-Frame (EOF)
2-4
ENUM/
4-7
exchanges transfer
2-2
Expansion ROM Base Address
F
fabric topology
2-8
FAULT0/
4-8
FAULT1/
4-8
FC
data structure
2-4
data traffic
3-1
devices
2-7
exchange
2-4
Fibre Channel
2-1
frames
2-4
interface
2-1
layer
2-2
link
1-9
N_Ports
2-3
sequence
2-4
structure
2-1
word
2-4
FCP
2-5
exchange
2-6
Fibre Channel Protocol
1-1
Fibre Channel (FC)
2-1
Fibre Channel Protocol (FCP)
Flash ROM read timing
6-20
Flash ROM write timing
6-21
FLASHCS/
4-10
2-4
2-8
5-19
1-1
IX-1
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