Read Commands - LSI LSIFC929 Technical Manual

5.3.3.5 PCI Target Disconnect

5.3.4 Read Commands

5.3.4.1 Memory Read Line
5.3.4.2 Memory Read Multiple
5.3.4.3 Memory Read
5-6
on another bus ownership. The chip issues another Write and Invalidate
command on the next ownership, in accordance with the
PCI specification.
During a Write and Invalidate transfer, if the target device issues a
disconnect the LSIFC929 relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip will not issue
another Write and Invalidate command on the next ownership unless the
address is aligned.
Memory Read Line and Memory Read Multiple commands are issued
with burst transfers where the memory system and the requesting master
may gain some performance advantage by prefetching read data. Cache
command usage is described below.
The Memory Read Line command is issued on any burst read of two or
more Dwords in which a cache line boundary is not crossed. The starting
address of the burst need not be aligned to a cache line boundary. This
command allows a capable bridge to prefetch and burst up to an entire
cache line of data, as opposed to disconnecting after every data phase.
The Memory Read Multiple command is issued on any burst read that
crosses a cache line boundary. The starting address of the burst need
not be aligned to a cache line boundary. This command allows a capable
bridge to prefetch multiple cache lines of data, maximizing read burst
potential.
For single Dword (nonburst) transfers, the Memory Read command is
used.
Registers
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