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3. Test Base Address Register
4. Request FIFO
The following Host Registers/Bits are unique and operate independently
with respect to Function[0] and Function[1]:
1. System Doorbell Register
2. Diagnostic Register (ResetHistory bit)
3. Host Interrupt Status Register
4. Host Interrupt Mask Register
5. Reply FIFO
6. Host Index Register
The Request FIFOs are internally combined between the two functions
due to the fact that both FIFOs are managed by the single IOP
microprocessor internal to the LSIFC929. A small piece of hardware logic
places a stamp onto Message Frame Address (MFA) bit 2 indicating from
which function the request originated. Unlike the Request FIFOs, the
Reply FIFOs are managed independently by the drivers associated with
each function. Therefore, separate hardware FIFOs are needed to
support each.
Register: 0x000
System Doorbell Register
Read/Write
31
0
0
0
0
15
0
0
0
0
The
to allow the System to pass single word messages to the embedded IOP
processor and vice versa. When a PCI master writes to the
HostRegs: Doorbell register, a maskable interrupt is generated to the IOP
processor. The value written by the System master is available for the
Host Interface Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
HDV (Most Significant)
0
0
0
0
HDV (Least Significant)
0
0
0
0
System Doorbell Register
0
0
0
0
0
0
0
0
is a simple message passing mechanism
16
0
0
0
0
0
0
0
0
0
5-25
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