LSI LSIFC929 Technical Manual page 50

Table 4.1 PCI Interface (Cont.)
Signal I/O
PERR/ S/T/S
SERR/ O
PAR T/S
PAR64 T/S
INTA/ O
INTB/ O
4-6
BGA Pad
Number Pad Type Description
AB7 5 V Tol
BiDir PCI
AC7 5 V Tol
BiDir PCI
AA8 5 V Tol
BiDir PCI
AA17 5 V Tol
BiDir PCI
U2 5 V Tol
BiDir PCI
U1 5 V Tol
BiDir PCI
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Parity Error may be pulsed active by an agent
that detects a parity error. PERR/ can be used
by any agent to signal data corruption.
However, on detection of a PERR/ pulse, the
central resource may generate a nonmaskable
interrupt to the host CPU, which often implies
the system will be unable to continue operation
once error processing is complete.
System Error is an open drain output used to
report address parity errors and data parity
errors on the Special Cycle command.
Parity is the even parity bit that protects the
AD[31:0] and C_BE[3:0]/ lines. During the
address phase, both the address and
command bits are covered. During the data
phase, both data and byte enables are covered.
Parity64 is the even parity bit that protects the
AD[63:32] and C_BE[7:4]/ lines. During the
address phase, both the address and
command bits are covered. During the data
phase, both data and byte enables are covered.
Interrupt A. This open-drain signal, when
asserted LOW, indicates that PCI Function[0] is
requesting service from its Host device driver. If
the chip is configured as a single-function
device, only INTA/ is used.
Interrupt B. This open-drain signal, when
asserted LOW, indicates that PCI Function[1] is
requesting service from its Host device driver. If
the chip is configured as a single-function
device, only INTA/ is used.