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3.1.1 Data Flows
Figure 3.1
LSIFC929 Block Diagram
SerDes
Tx
Link
Giga
Control
Blaze
Rx
Channel [0] ZBus
Channel [0]
SerDes
Tx
Link
Giga
Control
Blaze
Rx
Channel [1] ZBus
Channel [1]
3-2
Sequence and Exchange level. Error detection and I/O retries are also
handled by the LSIFC929, allowing the system to offload part of the
exception handling work from the system driver.
The LSIFC929 uses a 64-bit (33 MHz or 66 MHz) PCI interface to pass
control and data information between the system and the protocol
controller. This interface is managed by the PCI Interface block, as
shown in
Figure
3.1. It is backward compatible with 32-bit/33 or 66 MHz
buses.
Transmitter
Receiver
CtxMgr
ZArbiter
Transmitter
Receiver
CtxMgr
ZArbiter
For incoming serial data, the physical Link transfers the data to Link
Control using the GigaBlaze Integrated Transceiver. The Link Controller
analyzes the received frame and if appropriate, it passes the frame to the
LSIFC929 Overview
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Channel
DMA[0]
Arbiter/
Mux
DMA[1]
Zbridge
ZQman
Channel
Arbiter/
Mux
Zbridge
ZQman
PCI
PCI
Interface
Arbitrator
System
Interface
IOP
ZArbiter
TimerCfg
XMem
PBSRAM
PCI
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