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Table 4.3
Memory Interface
Signal
I/O
MD[31:0]
I/O
MD[31:24]
MP[3:0]
I/O
MA[21:0]
MOE[1:0]/
O
MWE[1:0]/
O
FLASHCS/
O
4-10
BGA Pad
Number
Pad Type Description
H22, H20, H21,
3.3 V
G23, G22, G21,
BiDir
F23, F22, E21,
4 mA
E23, E22, F21
D23, D22, C23,
D21, B18, A18,
C17, B17, A17,
C16, B16, A16
C15, B15, A15,
C14, D13, B14,
A14, C13
H23, B23, D18,
3.3 V
A13
4 mA
BiDir
w/pullup
R20, P21, R23,
3.3 V
R22, N20, P23,
BiDir
P22, N21, N23,
4 mA
N22, M23, M21
M22, L22, L21,
L23, K23, K22,
J23, K21, J22,
J21
B19, A19
3.3 V
BiDir
8 mA
B20, A20
3.3 V
BiDir
4 mA
C18
3.3 V
BiDir
4 mA
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
SSRAM Read/Write Data.
MD[31:24] are used for the FLASH ROM
Read/Write Data.
Memory Parity. Byte lane parity as follows:
MP [0]: Parity for MD[7: 0]
MP [1]: Parity for MD[15: 8]
MP [2]: Parity for MD[23:16]
MP [3]: Parity for MD[31:24]
Memory Parity may be optionally even, odd, or
none (not used) as defined in the LSIFC929
Programming Model.
SSRAM/FLASH ROM Address.
Memory Output Enable. When asserted LOW,
the selected SRAM or FLASH (MOE[1]/) device
may drive data. This signal is typically an
asynchronous input to SRAM and/or FLASH
devices. The two output enables allow for
interleaving configurations, with MOE[0]/ being
the only output enable used for a
noninterleaved implementation.
Memory Write Enables. These active LOW
bank write enables are required for interleaving
configurations. MWE[0]/ is the only write enable
used for a noninterleaved implementation.
FLASH Chip Select. This active-LOW chip
select allows connection of a single 8-bit
FLASH ROM device.
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