Host Interface Registers; Pci Memory 0 Address Map - LSI LSIFC929 Technical Manual

5.7 Host Interface Registers

Table 5.3

PCI Memory 0 Address Map

31
5-24
The first 128 bytes of PCI Memory 0 address space contain the Host
Interface Register set as specified in
accesses are allowed to the Host Register set. The LSIFC929 design
supports only nonburst accesses to the Host Interface Register Set and
will Disconnect-with-data (TRDY/ and STOP/ both asserted) after the first
transfer of any burst attempt.
The LSIFC929 also specifies an I/O space requirement of 128 bytes of
I/O mapped space which the System is required to assign during PCI
configuration. The 128 bytes of I/O space are mapped onto the first
128 bytes of Memory 0 space; they provide an alternate access path to
the Host Interface register set.
16 15
System Doorbell Register
Write Sequence Register
Host Diagnostic Register
Test Base Address Register
Reserved
Host Interrupt Status Register
Host Interrupt Mask Register
Reserved
Request FIFO
Reply FIFO
Reserved
Host Index Register
Reserved
SHARED MEMORY
The following Host Registers/Bits are shared (aliased) between
Function[0] and Function[1]:
1. Write Sequence Register
2. Diagnostic Register (except ResetHistory bit)
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Table 5.3. Both 32- and 64-bit
0
0x(Sizeof(Mem0)-1)
0x000
0x004
0x008
0x00C
0x010–0x02F
0x030
0x034
0x038–0x03F
0x040
0x044
0x048–0x04F
0x050
0x054–0x07F
0x080–