Operating Register Read - LSI LSIFC929 Technical Manual

Figure 6.3

Operating Register Read

CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master - Address;
LSIFC929 - Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master - Address;
LSIFC929 - Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSIFC929)
STOP/
(Driven by LSIFC929)
DEVSEL/
(Driven by LSIFC929)
t
1
t
1
Addr
In
t
1
CMD
t
2
Note: STOP/ is only asserted LOW if the Master attempts a burst
(i.e., FRAME/ is still asserted LOW).
AC Timing
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
t
2
t
2
Byte Enable
t
1
Addr
Parity
t
2
t
1
t
3
t
3
Data
Out
t
2
t
3
Data
Parity
t
2
t
3
t
3
Note 1
6-9