LSI LSIFC929 Technical Manual page 49

Table 4.1 PCI Interface (Cont.)
Signal I/O
FRAME/ S/T/S
IRDY/ S/T/S
TRDY/ S/T/S
DEVSEL/ S/T/S
STOP/ S/T/S
BGA Pad
Number Pad Type Description
AC5 5 V Tol
BiDir PCI
AA6 5 V Tol
BiDir PCI
AB6 5 V Tol
BiDir PCI
AC6 5 V Tol
BiDir PCI
AA7 5 V Tol
BiDir PCI
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Cycle Frame is driven by the current master to
indicate the beginning and duration of an
access. FRAME/ is asserted to indicate a bus
transaction is beginning. While FRAME/ is
deasserted, the transaction is in the final data
phase or the bus is idle.
Initiator Ready indicates the initiating agent's
(bus master's) ability to complete the current
data phase of the transaction. IRDY/ is used
with TRDY/. A data phase is completed on any
clock when both IRDY/ and TRDY/ are sampled
asserted. During a write, IRDY/ indicates that
valid data is present on AD[63:0]. During a
read, it indicates that the master is prepared to
accept data. Wait cycles are inserted until both
IRDY/ and TRDY/ are asserted together.
Target Ready indicates the target agent's
(selected device's) ability to complete the
current data phase of the transaction. TRDY/ is
used with IRDY/. A data phase is completed on
any clock when used with IRDY/. A data phase
is completed on any clock when both TRDY/
and IRDY/ are sampled asserted. During a
read, TRDY/ indicates that valid data is present
on AD[63:0]. During a write, it indicates that the
target is prepared to accept data. Wait cycles
are inserted until both IRDY/ and TRDY/ are
asserted together.
Device Select indicates that the driving device
has decoded its address as the target of the
current access. As an input, it indicates to a
master whether any device on the bus has
been selected.
Stop indicates that the selected target is
requesting the master to stop the current
transaction.
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