Pci Interface; 32-Bit Memory Controller; Lsifc929 Block Diagram - LSI LSIFC929 Technical Manual

Figure 1.2

LSIFC929 Block Diagram

SerDes
Tx
Link
Giga
Control
®
Blaze
Rx
Channel [0] ZBus
Channel [0]
SerDes
Tx
Link
Giga
Control
Blaze
Rx
Channel [1] ZBus
Channel [1]

1.3.1 PCI Interface

1.3.2 32-Bit Memory Controller

Transmitter
Receiver
CtxMgr ZArbiter
Transmitter
Receiver
CtxMgr ZArbiter
The LSIFC929 uses a 64-bit (33 MHz or 64 MHz) PCI interface or a
32-bit (33 MHz or 64 MHz) PCI interface. In addition, support is provided
for Dual Address Cycle (DAC), PCI power management, Subsystem
Vendor ID and Vendor Product Data (VPD). Extended access cycles
(MRL, MRM, MWI) are also supported.
The memory controller provides access to Flash ROM and 32-bit
Synchronous SRAM. It supports both interleaved and noninterleaved
configurations up to a maximum of 4 Mbytes of synchronous SRAM. A
Hardware Overview
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Channel
DMA[0]
Arbiter/
Mux
DMA[1]
Zbridge
ZQman
Channel
Arbiter/
Mux
Zbridge
ZQman
PCI
PCI
Interface
Arbitrator
System
Interface
IOP
ZArbiter
TimerCfg
XMem
PBSRAM
PCI
1-7