Message Flow - LSI LSIFC929 Technical Manual

Dual channel fibre channerl i/o processor
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3.2.2 Message Flow

3-4
information regarding the details of the message format, refer to the
LSI Logic Fusion-MPT specification.
Before Requests can be posted to the LSIFC929, the system must
allocate and initialize a pool of message frames, and provide a
mechanism to assign individual message frames, on a per-request basis.
The host must also provide one message frame per target LUN, and
prime the Reply Free FIFOs for each function with the physical address
of these message frames. Once allocation has been completed, requests
will flow from the host to the LSIFC929, as represented below and in
Figure
3.2.
1. The host driver receives an I/O request from the operating system.
2. The host driver allocates a system message frame and builds an I/O
request message within the SMF. The allocation method is the
responsibility of the host driver.
3. The host driver creates the Message Frame Descriptor (MFD), and
writes the MFD to the Request Post FIFO.
4. The IOC reads the MFD from the Request Post FIFO and DMA's the
request to a local message frame.
5. The IOC sends the appropriate Fibre Channel request, and
subsequently receives the reply from the target.
If the I/O status was successful, the IOC writes the
MessageContext value, plus turbo reply bits, to the Reply Post
FIFO, which automatically generates a system interrupt.
If the I/O status was not successful, the IOC pops a reply
message frame from the Reply Free FIFO, and generates a reply
message in the reply message frame. The IOC then writes the
system physical address of the reply message frame to the
Reply Post FIFO, which generates a system interrupt.
6. The host driver receives an interrupt and reads the Reply Register.
If there are no posted messages, the system reads the value
0xFFFFFFFF.
7. The host driver responds to the Operating System appropriately.
8. If the I/O status was not successful, the host driver returns it to the
Reply Free FIFO.
LSIFC929 Overview
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.

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