LSI LSIFC929 Technical Manual page 13

Dual channel fibre channerl i/o processor
Table of Contents

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6.6
4 mA Bidirectional Signals (LIPRESET/, ODIS1,
ODIS0, BYPASS1/, BYPASS0/, MD[31:0], MA[21:0],
MWE[1:0]/, FLASHCS/, BWE[3:0]/, RAMCS/, ZZ,
MP[3:0], SCL, SDA, RXLOS1, RXLOS0, ADSC/, ADV/,
TDO)
6.7
8 mA Bidirectional Signals (MODDEF1[2:0],
MODDEF0[2:0], GPIO[3:0], MOE[1:0]/, LED[4:0]/, MCLK)
6.8
6.9
PCI Bidirectional Signals (AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, STOP/, PERR/, PAR, ACK64/, ENUM/,
64EN/)
6.10
PCI Output Signals (PAR64, REQ/, REQ64/, DEVSEL/,
SERR/, INTA/, INTB/)
6.11
6.12
SSRAM Read/Write/Read Timings
6.13
6.14
6.15
6.16
6.17
A.1
LSIFC929 Multifunction PCI Registers
A.2
LSIFC929 Host Interface Registers
B.1
Contents
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
6-3
6-3
6-4
6-4
6-5
6-17
6-19
6-20
6-21
6-24
6-25
6-27
A-1
A-2
B-1
xiii

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