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31
0
0
0
15
0
0
0
5-26
IOP processor to read in the SysIfRegs: Doorbell register. The interrupt
status will be cleared when the IOP writes any value to the SysIfRegs:
DoorbellClear register. Conversely, when the IOP processor writes to the
SysIfRegs: Doorbell register, a maskable interrupt is generated to the
PCI system using the INTA/ signal pin. The value written by the IOP is
available to the System for reading from the HostRegs: Doorbell register.
The interrupt status/pin is cleared when the System writes any value to
the HostRegs: IntStatus register.
HDV
Host Doorbell Value (Read/Write)
Write: Doorbell value passed to IOP processor.
Read: Doorbell value received from IOP processor.
Register: 0x004
Write Sequence Register
Read/Write
0
0
0
0
R
0
0
0
0
The
Write Sequence Register
inadvertent writes to the
data specific writes must be written into the Write Sequence KEY field in
order to enable writes to the
written incorrectly causes the
looking for the first sequence value. The required data sequence is:
0x4, 0xB, 0x2, 0x7, 0xD
After the last value (0xD) is written, the
written to until another write occurs to the
any value). A bit is provided in the
indicates if write access has been enabled for the
Register
(e.g., to verify that the Write Sequence data sequence was
correct or to verify that writes to the
disabled).
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
R
0
0
0
0
0
0
0
0
provides a protection mechanism against
Host Diagnostic
Register. A sequence of five
Host Diagnostic
Write Sequence Register
Host Diagnostic Register
Host Diagnostic Register
Host Diagnostic Register
0
0
0
4
3
WSKEY
0
1
0
Register. Any data value
to restart by
Write Sequence Register
that
Host Diagnostic
have been
[31:0]
16
0
0
0
1
1
may be
(of
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