Ssram Read/Write/Read Timing Waveforms; Memory Interface Timings - LSI LSIFC929 Technical Manual

6.2.3 Memory Interface Timings

6.2.3.1 SSRAM Timings
Figure 6.11 SSRAM Read/Write/Read Timing Waveforms
MCLK
Addr(x)
MA/CTL
ADSC
Read
MD
Data
t
t
oev
olz
MOE[0]/
MOE[1]/
Rd Deselect Wr Address
& Select
& Bus Turn
Around
Table 6.12 SSRAM Read/Write/Read Timings
Symbol Parameter
t MCLK cycle time
cyc
t Read setup time
rsu
t Read hold time
rh
t Write valid time
wdv
t Write hold time
wdh
t Output enable valid
oev
t Data low impedance
olz
t Data high impedance
ohz
t Output enable nonoverlap
enov
1. The settings of FSELZ[1:0] determine the minimum and maximum MCLK cycle time. The values
shown above are for FSELZ[1:0] = 01 (MCLK = 70.833 MHz).
t
cyc
t
t wdh
wdv
Addr(y)
Addr(y)
ADSC
Invalid
Data(y)
Wr Data Wr Data
AC Timing
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Addr Addr(z)
Addr(z)
(y+1) ADSC
Data
(y+1)
t
ohz
Wr Deselect, Rd Pipe Wait
Rd Address,
& Select
Min
14.115
7
0
–
2
–
2.5
2
0
Addr
Addr(z)
(z+1)
t
rsu
Read
Read
Data(z+1)
Data(z)
t
rh
t
enov
Rd Data Rd Data
Max
1 1
14.119
–
–
10
–
8
12
12
–
Addr(z+2)
Read
Data(z+2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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