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31
0
0
0
15
0
0
0
5-28
between multiple driver instances in a multifunction PCI
implementation.
R
Reserved
Reserved for future use.
TTLI
TTL Interrupt (Read/Write)
This bit configures the PCI INTA/ pin as either open drain
or TTL. This bit defaults to '0' (open drain) on reset and
should only be set to '1' when the device is being tested
on a tester.
RA
Reset Adapter (Write Only)
When set to "1", this write only bit will cause a Soft Reset
condition within the LSIFC929 design. The bit is
self-cleared after eight PCI clock periods. After this bit is
deasserted, the IOP ARM will be executing from its
default Reset Vector.
DisARM
Disable ARM (Read/Write)
The DisARM bit when set to '1' causes the IOP ARM to
be held reset. This bit is used primarily to enable
downloading of code/data by a Host resident utility.
DME
Diagnostic Memory Enable (Read/Write)
This bit when set to '1' enables Diagnostic Memory
accesses using PCI Memory 1 address space. If
writes/reads to Memory 1 space are attempted with this
bit cleared to '0', they are properly terminated on the PCI
bus, but are not NOP'd by the chip.
Register: 0x00C
Test Base Address Register
Read/Write
0
0
0
0
0
0
0
0
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
TBAddr
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
16
0
0
0
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