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Table 4.2
Fibre Channel Interface
Signal
I/O
ODIS1
O
BYPASS0/
O
BYPASS1/
O
RXLOS0
I
RXLOS1
I
MODDEF0[2:0]
I
MODDEF1[2:0]
I
REFCLK
I
BGA Pad
Number
Pad Type
J1
3.3 V BiDir
4 mA
T1
3.3 V BiDir
4 mA
K3
3.3 V BiDir
4 mA
P3
3.3 V 4 mA
BiDir
w/pulldown
E1
3.3 V 4 mA
BiDir
w/pulldown
A9, C10,
3.3 V BiDir
D11
8 mA
w/pullup
B10, A10,
3.3 V BiDir
C11
8 mA
w/pullup
E2
3.3 V
Schmitt
Input
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Description
Output Disable, Channel1. This output when
asserted disables an external GBIC or MIA
transmitter for channel1. This output is also
used to clear a module fault.
This line is driven LOW when the LSIFC929
Link Controller block has determined that
channel0 of the device is operating in a loop
environment and the device has entered a
bypassed mode. This may be caused by an
internal request or a loop primitive generated
by another node.
This line is driven LOW when the LSIFC929
Link Controller block has determined that
channel1 of the device is operating in a loop
environment and the device has entered a
bypassed mode. This may be caused by an
internal request or a loop primitive generated
by another node.
This line is driven HIGH, disabling the on-chip
receiver, when the GBIC for channel0 of the
LSIFC929 has detected a loss of signal. If
enabled through the Link Control Register, this
signal becomes an output test strobe.
This line is driven HIGH, disabling the on-chip
receiver, when the GBIC for channel1 of the
LSIFC929 has detected a loss of signal. If
enabled through the Link Control Register, this
signal becomes an output test strobe.
GBIC and pluggable SFF optical module
Identifiers (channel0).
GBIC and pluggable SFF optical module
Identifiers (channel1).
FC reference clock (106.25 MHz ± 100 ppm).
4-9
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