Table of Contents
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frame
data
2-3
end of
2-4
link control
2-3
payload
2-6
start of
2-4
transfer
2-2
FRAME/
4-5
FSELZ[1:0]
4-12
functional block diagram
1-7
functional signal grouping
4-2
G
GigaBlaze transceiver
3-2
GNT/
4-3
GPIO[2](BLUELED/)
4-7
GPIO[3:0]
4-14
ground pins
4-16
H
Header
5-13
Host Diagnostic Register
5-27
Host Index Register
5-32
Host Interrupt Mask Register
Host Interrupt Status Register
HOTSWAPEN/
4-7
I
I/O Base Address
5-14
IDDTN
4-15
IDSEL
4-4
implementation 1-5,
3-8
initiator command sequence
input signals
6-2
INTA/
4-6
INTB/
4-6
integrated transceiver
1-8
integration
2-3
interface
FC
2-1
media
2-2
system
1-8
upper level protocol (ULP)
interface timing
PCI
6-17
SSRAM read/write/read
intermix class
2-10
internet protocol (IP)
2-1
Interrupt
5-21
IRDY/
4-5
L
LAN message interface
3-6
LAN protocol stack
3-7
Latency 5-13,
5-21
latency
5-5
LED[4:0]/
4-14
link control frames 2-3,
2-4
link controller
1-8
LIPRESET/
4-8
IX-2
5-30
5-29
2-6
2-1
6-19
Index
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
M
MA[21:0]
4-10
maximum ambient temperature
maximum stress ratings
6-1
MCLK
4-11
MD[31:0]
4-10
media interface
2-2
Mem0 Base Address High
5-16
Mem0 Base Address Low
5-15
Mem1 Base Address High
5-17
Mem1 Base Address Low
5-16
memory controller
1-7
memory read
5-6
memory read line command
memory read multiple
5-6
memory shared
5-32
Memory Write and Invalidate command
message flow
3-5
message interface
3-3
Message Queueing Models
message transport
1-8
MODE[7:0]
4-13
MODEF0[2:0]
4-9
MODEF1[2:0]
4-9
MOE[1:0]
4-10
MP[3:0]
4-10
multifunction PCI
5-8
multiple cache line transfers
MWE[1:0]/
4-10
O
ODIS0
4-8
ODIS1
4-9
operating conditions
6-2
overview
1-1
to
1-3
P
packaging 6-26,
6-27
PAR
4-6
PAR64
4-6
payload 2-4,
2-6
PCI bidirectional signals
6-4
PCI cache mode
5-3
memory read line command
Memory Write and Invalidate command
PCI commands
5-2
PCI configuration register map
PCI configuration registers
5-7
PCI configuration space
5-1
PCI input signals
6-4
PCI interface timing
6-17
PCI Memory 0 address map
PCI output signals
6-5
PCI target disconnect
5-6
PCI target retry
5-5
PCICLK
4-3
PERR/
4-6
pinout
6-22
point-to-point topology
2-8
ports
2-7
Power Management Configuration
Power Management Control
6-27
5-6
5-4
3-4
5-5
5-6
5-4
5-8
to
5-23
5-24
5-22
5-22
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