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6.2.3.2 FLASH Timings
Figure 6.12 FLASH ROM Read Timing Waveforms
MCLK
Addr(?)
MA
Read/Write
MD
Data
FLASHCS/
MOE[1]/
BWE[3]/
Idle or
M-STATE
S-Xfer
Table 6.13
FLASH ROM Read Timings
Symbol
Parameter
t
MCLK cycle time
cyc
t
Address setup time
as
t
Address hold time
ah
t
Read setup time
rs
t
Read hold time
rh
t
Data high impedance
hz
1. The settings of FSELZ[1:0] determine the minimum and maximum MCLK cycle time. The values
shown above are for FSELZ[1:0] = 01 (MCLK = 70.833 MHz).
2. Address setup time defaults to one (1) MCLK but may be programmed to zero (0) MCLKs using the
serial EEPROM.
6-20
t
cyc
Addr(x)
t
as
F-Addr
F-Addr
F-Wait(n)
n = 16
Specifications
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
t
rh
t
rs
Data(x)
t
ah
t
hz
F-Data
F-Turn
F-Turn
Min
1
14.115
− 5.0
2
0
7
0
0
Addr(y)
F-Addr
F-Addr
Max
Unit
1
14.119
ns
2
1 – MCLK
ns
–
ns
–
ns
–
ns
32
ns
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