LSI LSIFC929 Technical Manual page 83

Dual channel fibre channerl i/o processor
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Register: 0x03C/0x13C
Latency/Interrupt
Read/Write
31
MaxLat
0
0
0
0
15
IntPin
0
0
0
0
MaxLat
MinGnt
IntPin
IntLin
PCI/Multifunction PCI Configuration Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
24
0
0
0
0
8
0
0
X
X
Maximum Latency (Read Only)
This value has been set to a small number (0x08) to
request small latencies for PCI arbitration.
Minimum Grant (Read Only)
This value has been set to a large number (0x1E) to
indicate that the LSIFC929 is capable of large burst
transfers.
Interrupt Pin (Read Only)
This register tells which interrupt pin the device uses. Its
value is set at power-up to 0x01 for the INTA/ signal
(Function[0]), or 0x02 for the INTB/ signal (Function[1]).
Interrupt Line (Read/Write)
This register is used to communicate interrupt line routing
information. POST software will write the routing
information into this register as it initiates and configures
the system. The value in this register tells which input of
the system interrupt controller(s) the device's interrupt pin
has been connected to. Values in this register are
specified by system architecture.
23
MinGnt
0
0
0
0
7
IntLin
0
0
0
0
16
0
0
0
0
0
0
0
0
0
[31:24]
[23:16]
[15:8]
[7:0]
5-21

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