LSI LSIFC929 Technical Manual page 78

Dual channel fibre channerl i/o processor
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31
0
0
0
15
0
0
0
31
0
0
0
15
0
0
0
0
5-16
Register: 0x018
Mem0 Base Address High
Read/Write
Mem0BAddH (Most Significant)
0
0
0
0
Mem0BAddH (Least Significant)
0
0
0
0
Mem0BAddH Mem0 Base Address High (Read/Write)
Indicates upper 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
This allows the LSIFC929 to be mapped above the
4 Gbytes boundary.
Register: 0x01C
Mem1 Base Address Low
Read/Write
Mem1BAddL (Most Significant)
0
0
0
0
Mem1BAddL (Least Significant)
0
0
0
Mem1BAddL Mem0 Base Address Low (Read/Write)
Indicates lower 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
Its size is programmable from 16 Kbytes (2
512 Kbytes (2
[27:24] of the PCI Config0 register). The default value
indicated is 64 Kbytes, unless firmware programs a differ-
ent value prior to PCI configuration, or if programmed
with the serial EPROM.
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
19
) in steps of powers of 2 (based on bits
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
Prefetch
Type
0
0
1
0
14
) through
16
0
0
0
[31:0]
16
0
0
IOMemSp
0
[31:4]

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