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Figure 6.2
Configuration Register Write
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master - Address;
LSIFC929 - Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master - Address;
LSIFC929 - Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSIFC929)
STOP/
(Driven by LSIFC929)
DEVSEL/
(Driven by LSIFC929)
IDSEL
(Driven by Master)
6-8
t
1
t
2
t
1
Addr
In
t
2
t
1
CMD
t
2
t
1
Note: STOP/ is only asserted LOW if the Master attempts a burst
(i.e., FRAME/ is still asserted LOW.)
Specifications
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
t
1
Data In
t
1
Byte Enable
t
1
Addr
Parity
t
2
t
1
t
3
t
3
Note 1
t
3
t
2
t
2
t
2
t
1
Data
Parity
t
2
t
2
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