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Table 4.4
Configuration Signals
Signal
I/O
ROMSIZE
I
[1:0]
TESTRESET/ I
ARMEN/
I
FSELZ[1:0]
I
4-12
BGA Pad
Number
Pad Type Description
C12, A12
3.3 V TTL
Input
w/pullup
A11
3.3 V
Schmitt
Input
w/pullup
B13
3.3 V TTL
Input
w/pullup
A3, B4
3.3 V TTL
Input
w/pullup
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
This field identifies the size of the ROM that is
connected to the device. The value of this bus should
be established at chip reset and should remain
unchanged until another chip reset. The encoding of
this field is as follows:
Bits [1:0] ROM Size
00
256 Kbytes
01
512 Kbytes
10
1024 Kbytes
11
No external memory present
Test Reset. This pin forces the chip into the
Power-On-Reset state or Soft-Reset state, depending
on the state of the Mode pins.
When this pin is asserted LOW, the ARM RISC
processor core (IOP) is enabled and will boot from
FLASH ROM following chip reset. If this configuration
pin is held high, the IOP core will be held reset until
the DisARM bit in the Diagnostic register is cleared
by the Host CPU.
Frequency Select. These pins indicate how the
RefClk input (106.25 MHz) is internally divided to
generate the internal ZClk source. When FSELZ[1] is
HIGH, the internal ZClk tree is sourced directly from
the ZCLK input signal.
FSELZ[1:0]
Internal ZClk
00
REFCLK/2
01
REFCLK * 2/3
10
External ZCLK
11
External ZCLK
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