LSI LSIFC929 Technical Manual page 67

5.3.3.2 Multiple Cache Line Transfers
5.3.3.3 Latency
5.3.3.4 PCI Target Retry
1. The PCI configuration
2. The Cache Line Size
8, 16, 32, 64, or 128) value.
3. The chip must have enough bytes in the DMA FIFO to complete at
least one full cache line burst.
4. The chip must be aligned to a cache line boundary.
When these conditions have been met, the LSIFC929 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
The Memory Write and Invalidate command can write multiple cache
lines of data in a single bus ownership. The chip issues a burst transfer
as soon as it reaches a cache line boundary. The size of the transfer will
not automatically be the cache line size, but rather a multiple of the
cache line size as allowed for in the Revision 2.1 of the PCI specification.
The logic selects the largest multiple of the cache line size based on the
amount of data to transfer.
When the DMA buffer contains less data than the value specified in the
Cache Line Size register, the LSIFC929 throttles back to a Memory Write
command on the next cache line boundary.
In accordance with the PCI specification, the chip's latency timer is
ignored when issuing a Write and Invalidate command. When a latency
time-out has occurred and GNT/ is deasserted, the LSIFC929 continues
to transfer up until a cache line boundary. At that point, the chip
relinquishes the bus, and finishes the transfer at a later time using
another bus ownership. In accordance with the PCI Local Bus
Specification, the latency timer is completely ignored as long as GNT/ is
asserted to the LSIFC929.
During a Write and Invalidate transfer, if the target device issues a retry
(STOP with no TRDY, indicating that no data was transferred), the
LSIFC929 relinquishes the bus and immediately tries to finish the transfer
PCI Cache Mode
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Command register, bit 4 must be set.
register must contain a legal burst size (2, 4,
5-5