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31
30
29
28
DPE
SSE
MA
RTA
0
0
0
15
R
0
0
0
5-10
Register: 0x004
Status/Command
Read/Write
27
26
25
R
DevSEL/Tim DPR
0
0
0
1
9
0
0
0
0
The most significant half of the
record status information for PCI bus-related events.
Reads to the upper half of this register (status) behave normally. Writes
are slightly different in that bits can be cleared, but not set. A bit is reset
whenever the register is written, and the data in the corresponding bit
location is a one. For instance, to clear bit 31 and not affect any other
bits, write the value 0x8000 to the register.
The least significant half of the
coarse control over a device's ability to generate and respond to PCI
cycles. When a zero is written to this register, the LSIFC929 is logically
disconnected from the PCI bus for all accesses except configuration
accesses.
DPE
Detected Parity Error (Read/Write)
This bit will be set by the LSIFC929 whenever it detects
a data parity error, even if parity error handling is
disabled.
SSE
Signaled System Error (Read/Write)
This bit is set whenever a device asserts the SERR/
signal.
MA
Master Abort (Read/Write)
This bit should be set by a master device whenever its
transaction (except for Special Cycle) is terminated with
master abort. All master devices should implement this
bit.
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
24
23
0
0
0
0
8
7
6
5
SERR
R
EPER
R
0
0
0
0
Status/Command
Status/Command
R
0
0
0
0
4
3
2
1
WIM
R
EBM
EMS EIOS
0
0
0
0
Register is used to
Register provides
16
0
0
0
31
30
29
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