Pci Interface - LSI LSIFC929 Technical Manual

Table 4.1

PCI Interface

Signal I/O
PCICLK I
RST/ I
GNT/ I
REQ/ O
REQ64/ O
ACK64/ S/T/S
BGA Pad
Number Pad Type Description
AA13 5 V Tol In Clock provides timing for all transactions on the
T3 5 V Tol In Reset forces the PCI sequencer of the device
V1 5 V Tol
BiDir PCI
V2 5 V Tol
BiDir PCI
AA15 5 V Tol
BiDir PCI
Y15 5 V Tol
BiDir PCI
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
PCI bus and is an input to every PCI device. All
other PCI signals are sampled on the rising
edge of PCICLK, and other timing parameters
are defined with respect to this edge.
to a known state. All 3-state and sustained
3-state signals are forced to a high impedance
state, and all internal logic is reset. The RST/
input is synchronized internally to the rising
edge of PCICLK. The PCICLK input must be
active while RST/ is asserted to properly reset
the device.
Grant indicates to the agent that access to the
PCI bus has been granted. This is a
point-to-point signal. Every master has its own
GNT/.
Request indicates to the system arbiter that
this agent desires use of the PCI bus. This is a
point-to-point signal. Every master has its own
REQ/.
Request64 indicates that the current bus
master desires to transfer data using 64 bits.
REQ64/ is sampled at the end of reset to
indicate the presence of a 64-bit bus.
Acknowledge64 is an input from the Target
that decodes the address, and indicates that
the Target is willing to complete a 64-bit
transfer. No slaves on the LSIFC929 assert this
pin (i.e., all slaves are 32-bit slaves). The
LSIFC929 will not assert this pin when
accessed as a Target, but will monitor this pin
when initiating transfers (i.e., the LSIFC929
presents itself as a 32-bit slave device, but
operates as a 64-bit bus master).
4-3