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Operation
Ordered Set
Originator
Parity Checking
PCI
PDB
PIO
Port
Port Address
Port Number
RAM
Responder
RISC Core
A term, defined in FC-2, that refers to one of the FC "building blocks"
composed of one or more, possibly concurrent, exchanges.
A FC term referring to four 10-bit characters (a combination of data and
special characters) that provide low level link functions, such as frame
demarcation and signaling between two ends of a link. It provides for
initialization of the link after power-on and for some basic recovery
actions.
A FC term referring to the initiating device.
A way to verify the accuracy of data transmitted over the SCSI bus. One
bit in the transfer is used to make the sum of all the 1 bits either odd or
even (for odd or even parity). If the sum is not correct, an error message
appears.
Peripheral Component Interconnect. A local bus specification that allows
connection of peripherals directly to computer memory. It bypasses the
slower ISA and EISA buses.
Packet Descriptor Block
Programmed Input/Output. A way the CPU can transfer data to and from
memory using the computer's I/O ports. PIO is usually faster than DMA,
but requires CPU time.
The hardware entity within a node that performs data communications
over the FC link.
Also Port Number. The address through which commands are sent to a
host adapter board. This address is assigned by the PCI bus.
See Port Address.
Random Access Memory. The computer's primary working memory in
which program instructions and data are stored and are accessible to the
CPU. Information can be written to and read from RAM. The contents of
RAM are lost when the computer is turned off.
A FC term referring to the answering device.
LSIFC929 chips contain a RISC (Reduced Instruction Set Computer)
processor, programmed through microcode scripts.
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
C-5
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