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RTA
Received Target Abort (Read/Write)
This bit should be set by a master device whenever its
transaction is terminated with a target abort. All master
devices should implement this bit.
R
Reserved
Reserved for future use.
DevSEL/Tim
DevSEL/Timing (Read/Write)
These bits encode the timing of DEVSEL/. These are
encoded as:
0b00
0b01
0b10
0b11
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the LSIFC929, medium (0b01) is supported.
DPR
Data Parity Reported (Read/Write)
This bit is set when the following three conditions are
met:
–
The bus agent asserted PERR/ itself or observed PERR/
asserted;
–
The agent setting this bit acted as the bus master for the
operation in which the error occurred;
–
The Parity Error Response bit in the
is set.
R
Reserved
Reserved for future use.
SERR
SERR/Enable (Read/Write)
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is clear. The default value of this bit is zero.
This bit and bit 6 must be set to report address parity
errors.
R
Reserved
Reserved for future use.
PCI/Multifunction PCI Configuration Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
fast
medium
slow
reserved
28
27
[26:25]
24
Command
register
[23:9]
8
7
5-11
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