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power pins
4-16
PROC_DRVLS
4-15
processor
ARM RISC 1-6, 1-8,
1-9
I/O
1-8
protocol
channel
2-1
fibre channel (FCP) 1-1,
internet
2-1
signaling
2-2
transmission
2-2
upper level
2-1
protocols
upper layer
2-3
R
RAMCS/
4-11
receiver
1-9
REFCLK
4-9
reference specifications
B-1
register map A-1,
A-2
memory 0
5-24
PCI
5-8
Reply FIFO
5-31
reply message
3-3
REQ/
4-3
REQ64/
4-3
Request FIFO
5-31
request message
3-3
request status
1-9
response sequence
2-6
Revision ID
5-13
ROMSIZE [1:0]
4-12
RST/
4-3
RTRIM
4-8
RX0neg
4-8
RX0pos
4-8
RX1neg
4-8
RX1pos
4-8
RXLOS0
4-9
RXLOS1
4-9
S
Schmitt input signals
6-3
SCL
4-14
SCSI message interface
3-5
SDA
4-14
sequences transfer
2-2
SERR/
4-6
shared memory
5-32
signal names 6-24,
6-25
signaling protocol
2-2
SSRAM Memory
3-8
Start-of-Frame (SOF)
2-4
Status 5-10,
5-22
STOP/
4-5
Subsystem ID
5-18
Support Components
3-8
Flash ROM
3-9
Serial EEPROM
3-9
SSRAM Memory
3-8
SWITCH/
4-7
System Doorbell Register
5-25
system interface
1-8
2-5
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
T
target message class
3-7
target operation
1-9
target response
2-6
TCK
4-15
TDI
4-15
TDO
4-15
Test Base Address Register
TESTRESET/
4-12
timing diagram
64-bit dual-address cycle
64-bit initiator and 64-bit target (read)
back-to-back (read)
6-11
back-to-back (write)
6-12
burst (read)
6-13
burst (write)
6-14
configuration register (read)
configuration register (write)
Flash ROM read
6-20
Flash ROM write
6-21
operating register (read)
operating register (write) 6-8,
SSRAM read/write/read
TMS_CHIP
4-15
TMS_ICE
4-15
topology
arbitrated loop
2-7
fabric
2-7
point-to-point
2-7
transceiver 1-8,
3-2
transfer
exchanges
2-2
frames
2-2
sequences
2-2
transmission protocol
2-2
transmitter
1-9
TRDY/
4-5
TRST
4-15
TX0neg
4-8
TX0pos
4-8
TX1neg
4-8
TX1pos
4-8
U
upper layer protocols (ULPs)
V
Vendor ID 5-9,
5-18
W
Write Sequence Register
5-26
Z
ZCLK
4-14
ZZ
4-11
5-28
6-16
6-15
6-7
6-8
6-9
6-10
6-19
2-3
IX-3
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