LSI LSIFC929 Technical Manual page 12

Tables
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3.3 LAN Protocol Stack
3.4 LSIFC929 Typical Implementation
4.1 LSIFC929 Functional Signal Grouping
6.1 Configuration Register Read
6.2 Configuration Register Write
6.3 Operating Register Read
6.4 Operating Register Write
6.5 Back-to-Back Read
6.6 Back-to-Back Write
6.7 Burst Read
6.8 Burst Write
6.9 Read With 64-Bit Initiator and 64-Bit Target
6.10 64-Bit Dual-Address Cycle
6.11 SSRAM Read/Write/Read Timing Waveforms
6.12 FLASH ROM Read Timing Waveforms
6.13 FLASH ROM Write Timing Waveforms
6.14 LSIFC929 Pinout (329-Pin BGA) Top View
6.15 329-Pad Plastic Ball Grid Array
4.1 PCI Interface
4.2 Fibre Channel Interface
4.3 Memory Interface
4.4 Configuration Signals
4.5 Miscellaneous Signals
4.6 JTAG Test and I/O Processor Debug
4.7 Power and Ground Pins
5.1 PCI Bus Commands and Encoding Types
5.2 LSIFC929 PCI Configuration Register Map
5.3 PCI Memory 0 Address Map
6.1 Absolute Maximum Stress Ratings
6.3 Capacitance
6.4 Input Signals (FAULT1/, FAULT0/, ROMSIZE[1:0],
ARMEN/, FSELZ[1:0], MODE[7:0], SWITCH,
HOTSWAPEN/)
6.2 Operating Conditions
6.5 Schmitt Input Signals (REFCLK, TESTRESET/, ZCLK,
TCK, TDI, TRST/, TMS_CHIP, TMS_ICE)
Contents
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
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