LSI LSIFC929 Technical Manual page 74

5-12
EPER Enable Parity Error Response (Read/Write)
This bit allows the LSIFC929 to detect parity errors on the
PCI bus and report these errors to the system. Only data
parity checking is enabled. The LSIFC929 always
generates parity for the PCI bus.
R Reserved
Reserved for future use.
WIM Write and Invalidate Mode (Read/Write)
This bit, when set, will cause Memory Write and
Invalidate cycles to be issued on the PCI bus after certain
conditions have been met. For more information on these
conditions, refer to
Invalidate
R Reserved
Reserved for future use.
EBM Enable Bus Mastering (Read/Write)
This bit controls the LSIFC929's ability to act as a master
on the PCI bus. A value of zero disables the device from
generating PCI bus master accesses. A value of one
allows the LSIFC929 to behave as a bus master.
EMS Enable Memory Space (Read/Write)
This bit controls the LSIFC929's response to Memory
Space accesses. A value of zero disables the device
response. A value of one allows the LSIFC929 to respond
to Memory Space accesses at the address specified by
the Memory Base Address registers in the PCI
configuration space.
EIOS Enable I/O Space (Read/Write)
This bit controls the LSIFC929's response to I/O space
accesses. A value of zero disables the response. A value
of one allows the LSIFC929 to respond to I/O space
accesses at the address specified in I/O Base Address
register in the PCI configuration space.
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Section 5.3.3, "Memory Write and
Command".
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