Table of Contents
Advertisement
31
0
0
0
15
IOBAdd (Least Significant)
0
0
0
0
5-14
BIST
Built-In Self Test (Read Only)
HdTyp
Header Type (Read Only)
This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions. The value of this
register is 0x80, indicating the LSIFC929 is a
multifunction controller.
LatTim
Latency Timer (Read/Write)
The
clocks, the value of the Latency Timer for this PCI bus
master. The LSIFC929 supports this timer. All eight bits
are writable, allowing latency values of 0–255 PCI clocks.
Use the following equation to calculate an optimum
latency value for the LSIFC929:
Latency = 2 + (Burst Size * (typical wait states +1)).
Values other than optimum are also acceptable.
Cache
Cache Line Size (Read/Write)
This register specifies the system cache line size in units
of 32-bit words. For more information on this register, see
Section 5.3.1, "Support for PCI Cache Line Size
Register".
Register: 0x010
I/O Base Address
Read/Write
IOBAdd (Most Significant)
0
0
0
0
0
0
0
Note that this register is only 32 bits, because I/O must be mapped into
the lower 4 Gbytes of address space.
Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Latency Timer
register specifies, in units of PCI bus
0
0
0
8
7
0
0
0
0
0
0
0
0
R
0
0
0
[31:24]
[23:16]
[15:8]
[7:0]
16
0
0
1
0
IOMemSp
0
1
Advertisement
Table of Contents
