Flash Rom Write Timing Waveforms; Flash Rom Write Timings - LSI LSIFC929 Technical Manual

Figure 6.13 FLASH ROM Write Timing Waveforms
MCLK
Addr(?
MA
Read/Write
MD
Data
FLASHCS/
MOE[1]/
BWE[3]/
Idle or
M-STATE
S-Xfer
Table 6.14

FLASH ROM Write Timings

Symbol Parameter
t MCLK cycle time
cyc
t Address setup time
as
t Address hold time
ah
t Write setup time
ws
t Write hold time
wh
1. The settings of FSELZ[1:0] determine the minimum and maximum MCLK cycle time. The values
shown above are for FSELZ[1:0] = 01 (MCLK = 70.833 MHz)
2. Address setup time defaults to one (1) MCLK but may be programmed to zero (0) MCLKs using the
serial EEPROM.
3. Programmed using the serial EEPROM.
t
cyc
t
as
F-Addr F-Addr F-Wait(n)
n = 16
AC Timing
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Addr(x)
t
Data(x)
t
t
ws
F-Data F-Turn
Min
1
14.115
− 5.0
2
1 MCLK
3
3
1 – MCLK
ah
wh
Idle F-Addr F-Addr
Max
1
14.119
2
1 – MCLK
–
3
11
–
Addr(y)
Data(y)
Unit
ns
ns
ns
MCLK
ns
6-21