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5.1 PCI Addressing
Chapter 5
Registers
This chapter provides a description of the registers in the LSIFC929
Fibre Channel PCI Protocol Controller chip. The chapter contains the
following sections:
•
Section 5.1, "PCI Addressing"
•
Section 5.2, "PCI Bus Commands Supported"
•
Section 5.3, "PCI Cache Mode"
•
Section 5.4, "Unsupported PCI Commands"
•
Section 5.5, "Programming Model"
•
Section 5.6, "PCI/Multifunction PCI Configuration Registers"
•
Section 5.7, "Host Interface Registers"
•
Section 5.8, "Shared Memory"
There are three types of PCI-defined address space:
•
Configuration space
•
Memory space
•
I/O space
Configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each "slot" or "stub" on the bus. Decoding C_BE[7:0]/
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a "chip select" that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL will be ignored. The eight lower order addresses are used to
select a specific 8-bit register. AD[10:8] are decoded as well, but they
LSIFC929 Dual Channel Fibre Channel I/O Processor
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
5-1
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