LSI LSIFC929 Technical Manual page 89

Dual channel fibre channerl i/o processor
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R
WSKEY
Register: 0x008
Host Diagnostic Register
Read/Write
31
0
0
0
0
15
0
0
0
0
The
status information.
R
DWE
FBS
RH
Host Interface Registers
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Reserved
Reserved for future use.
Write Sequence KEY (Read/Write)
KEY field for Write Sequence as described above.
0
0
0
R
0
0
0
Host Diagnostic Register
Reserved
Reserved for future use.
Diagnostic Write Enable (Read Only)
This bit, when set to '1', indicates that write access to the
Host Diagnostic Register
result of writing the correct key sequence into the
Sequence
Flash Bad Signature (Read Only)
This bit, when set to '1', indicates that the IOP ARM
processor has attempted to boot from FLASH ROM but
encountered a bad FLASH signature. When this occurs,
the DisARM bit in this register is set to '1' (holding the
IOP ARM reset) until both the FlashBadSignature and
DisARM conditions are cleared by the Host.
Reset History
This bit, when set to '1', indicates that physical reset
(POR, PCI, or Test Reset/) has occurred within the
LSIFC929 device. This bit may be written to zero by a
Host driver to help coordinate error/reset recovery
R
0
0
0
0
8
7
6
5
DWE
FBS
RH
0
0
0
0
contains low level diagnostic controls and
may occur. This bit is set as a
Register.
0
0
0
0
4
3
2
1
R
TTLI
RA
DisARM DME
0
0
0
x
[31:4]
[3:0]
16
0
0
0
[31:8]
7
Write
6
5
5-27

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