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Table 4.1
PCI Interface (Cont.)
Signal
I/O
AD[63:0]
T/S
C_BE[7:0]/
T/S
IDSEL
I
4-4
BGA Pad
Number
Pad Type Description
AC18, AB18,
5 V Tol
AA18, AC19
BiDir PCI
AB19, AA19,
AC20, AB20
AC21, AA20,
AC22, AB21
AC23, AB22,
AA22, AB23
AA23, Y22,
Y23, W21
W22, W23,
V21, V22
V23, U22, U23,
T21, T20, T22,
T23, R21
V3, W1, W2,
W3, Y1, Y2,
AA1, AB1
AB2, AB3,
AC2, AA4,
AC3, AB4,
AC4, AA5
AC8, AA9,
AB9, AC9,
AA10, Y11,
AB10, AC10,
AC11, AB11,
AC12, AB14,
Y13, AA14,
AC15, AB15
AC16, AB16,
5 V Tol
AC17, AB17,
BiDir PCI
AA2, AB5,
AB8, AA11
AC1
5 V Tol
BiDir PCI
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
The physical longword Address and Data are
multiplexed on the same PCI pins. During the
first clock of a transaction, AD[63:0] contains a
physical byte address. During subsequent
clocks, AD[63:0] contains data. A bus
transaction consists of an address phase
followed by one or more data phases. PCI
supports both read and write bursts. AD[7:0]
define the least significant byte, and AD[63:56]
define the most significant byte.
Bus Command and Byte Enables are
multiplexed on the same PCI pins. During the
address phase of a transaction, C_BE[3:0]/
define the bus command. During the data
phase, C_BE[7:0]/ are used as byte enables.
The byte enables determine which byte lanes
carry meaningful data. C_BE[0]/ applies to the
least significant byte, and C_BE[7]/ to the most
significant byte. Byte enables are active LOW.
Initialization Device Select is used as a chip
select in place of the upper 24 address lines
during configuration read and write
transactions.
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