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6.2 AC Timing
6.2.1 PCI Interface Timing Diagrams
6-6
The AC characteristics described in this section apply over the entire
range of operating conditions. Chip timings are based on simulation at
worst case voltage, temperature, and processing. Timings were
developed with a load capacitance of 50 pF.
Figure 6.1
through
Figure 6.8
LSIFC929 accesses the PCI bus. The timings for the PCI bus are listed
on
page
6-17. The LSIFC929 conforms to Revision 2.1 of the PCI Local
Bus Specification. The timing specifications are provided here for ease
of reference only.
Timing diagrams included in this section:
•
Configuration Register Read
•
Configuration Register Write
•
Operating Register Read
•
Operating Register Write
•
Back-to-Back Read
•
Back-to-Back Write
•
Burst Read
•
Burst Write
•
Read With 64-Bit Initiator and 64-Bit Target
•
64-Bit Dual-Address Cycle
Specifications
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
represent signal activity when the
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