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Manuals and User Guides for LSI LSI53C1000. We have
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LSI LSI53C1000 manual available for free PDF download: Technical Manual
LSI LSI53C1000 Technical Manual (384 pages)
PCI to Ultra160 SCSI Controller
Brand:
LSI
| Category:
Controller
| Size: 4 MB
Table of Contents
Table of Contents
7
Chapter 1 Introduction
17
General Description
17
New Features in the LSI53C1000
19
Typical LSI53C1000 System Application
19
Benefits of Ultra160 SCSI
20
Benefits of Surelink (Ultra160 SCSI Domain Validation)
21
Benefits of Lvdlink
22
Benefits of Tolerant ® Technology
22
Summary of LSI53C1000 Benefits
23
SCSI Performance
23
PCI Performance
25
Integration
25
Ease of Use
26
Flexibility
26
Reliability
27
Testability
27
Chapter 2 Functional Description
29
LSI53C1000 Block Diagram
30
PCI Functional Description
31
PCI Addressing
31
PCI Bus Commands and Functions Supported
32
PCI Bus Commands and Encoding Types
32
PCI Cache Mode
38
PCI Cache Mode Alignment
39
SCSI Functional Description
46
SCRIPTS Processor
47
Internal SCRIPTS RAM
47
64-Bit Addressing in SCRIPTS
48
Hardware Control of SCSI Activity LED
49
Designing an Ultra160 SCSI System
50
New Phases on SCSI Bus
51
Prefetching SCRIPTS Instructions
59
Opcode Fetch Burst Capability
60
Load and Store Instructions
60
JTAG Boundary Scan Testing
61
Parity/Crc/Aip Options
61
Bits Used for Parity/Crc/Aip Control and Generation
62
SCSI Parity Errors and Interrupts
63
Dma Fifo
64
SCSI Data Paths
65
LSI53C1000 Host Interface SCSI Data Paths
65
SCSI Bus Interface
67
Select/Reselect During Selection/Reselection
68
Synchronous Operation
69
SCF Divisor Values
70
Interrupt Handling
73
Determining the Synchronous Transfer Rate
73
Interrupt Routing
81
Interrupt Routing Hardware Using the LSI53C1000
82
Chained Block Moves
83
Chained Block Move Instruction
83
Parallel ROM Interface
87
Parallel ROM Support
88
Serial EEPROM Interface
89
Default Download Mode
89
Default Download Mode Serial EEPROM Data Format
89
No Download Mode
90
Power Management
90
Power State D0
91
Power State D1
91
Power States
91
Power State D2
92
Power State D3
92
Chapter 3 Signal Descriptions
93
Signal Organization
93
LSI53C1000 Signal Grouping
95
Internal Pull-Ups and Pull-Downs on LSI53C1000 Signals
96
PCI Bus Interface Signals
96
LSI53C1000 Internal Pull-Ups and Pull-Downs
96
System Signals
97
Address and Data Signals
98
Interface Control Signals
99
Arbitration Signals
100
Error Reporting Signals
100
Interrupt Signals
101
SCSI Bus Interface Signals
101
SCSI Signals
102
SCSI Control Signals
104
General Purpose I/O (GPIO) Signals
105
Flash ROM and Memory Interface Signals
106
Test Interface Signals
107
Power and Ground Signals
108
MAD Bus Programming
109
MAD[3:1] Pin Decoding
110
Chapter 4 Registers
111
PCI Configuration Registers
111
PCI Configuration Register Map
112
SCSI Registers
131
SCSI Register Map
132
SCSI Shadow Registers
139
Maximum Synchronous Offset
144
Chapter 5 SCSI SCRIPTS Instruction Set
147
Scsi Scripts
147
Second Dword
170
Single Transition Transfer Waveforms
212
DT Transfer Waveforms (XCLKS Examples)
213
DT Transfer Waveforms (XCLKH Examples)
214
DT Transfer Rates
215
Single Transition Transfer Rates
216
Sample Operation
237
Block Move Instructions
238
SCRIPTS Overview
238
First Dword
239
Block Move Instruction - First Dword
239
Second Dword
247
Block Move Instruction - Second Dword
247
Third Dword
248
I/O Instructions
248
First Dword
248
Block Move Instruction - Third Dword
248
First 32-Bit Word of the I/O Instruction
248
Read/Write Instructions
248
Second Dword
256
Second 32-Bit Word of the I/O Instruction
256
Read/Write Instructions
257
First Dword
257
Read/Write Instruction - First Dword
257
Second Dword
258
Read-Modify-Write Cycles
258
Move To/From SFBR Cycles
259
Transfer Control Instructions
261
First Dword
261
Second Dword
267
Third Dword
267
Transfer Control Instructions - Second Dword
267
Memory Move Instructions
268
Read/Write System Memory from a SCRIPT
269
Second Dword
270
Third Dword
270
Load and Store Instructions
271
First Dword
272
Second Dword
273
Load and Store Instructions - Second Dword
274
Chapter 6 Specifications
275
DC Characteristics
275
Absolute Maximum Stress Ratings
276
LVD Driver
277
LVD Receiver
278
Ma Bidirectional Signals—Gpio0_Fetch GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
279
Frame/, Irdy/, Trdy/, Devsel/, Stop/, Perr Par, Par64, Req64/, Ack64/
280
Tolerant Technology Electrical Characteristics
281
Rise and Fall Time Test Condition
282
Hysteresis of SCSI Receivers
283
Output Current as a Function of Output Voltage
284
AC Characteristics
285
External Clock
285
Reset Input
286
PCI and External Memory Interface Timing Diagrams
287
Target Timing
288
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle
288
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Read Cycle
288
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Write Cycle
288
Slow Memory (≥ 128 Kbytes) Read Cycle
288
Slow Memory (≥ 128 Kbytes) Write Cycle
288
Kbytes ROM Read Cycle
288
Kbytes ROM Write Cycle
288
PCI Configuration Register Read
289
PCI Configuration Register Write
290
Operating Registers/Scripts RAM Read, 32 Bits
291
Operating Register/Scripts RAM Read, 64 Bits
292
Operating Register/Scripts RAM Read, 64 Bits
293
Operating Register/Scripts RAM Read, 32 Bits
294
Operating Register/Scripts RAM Write, 32 Bits
295
Operating Register/Scripts RAM Write, 64 Bits
296
Operating Register/Scripts RAM Write, 64 Bits
297
Initiator Timing
298
Nonburst Opcode Fetch, 32-Bit Address and Data
299
Burst Opcode Fetch, 32-Bit Address and Data
300
Burst Opcode Fetch, 32-Bit Address and Data
301
Back to Back Read, 32-Bit Address and Data
302
Back to Back Read, 32-Bit Address and Data
303
Back to Back Write, 32-Bit Address and Data
304
Back to Back Write, 32-Bit Address and Data
305
Burst Read, 32-Bit Address and Data
306
Burst Read, 32-Bit Address and Data
307
Burst Read, 64-Bit Address and Data
308
Burst Read, 64-Bit Address and Data
309
Burst Write, 32-Bit Address and Data
310
Burst Write, 32-Bit Address and Data
311
Burst Write, 64-Bit Address and Data
312
Burst Write, 64-Bit Address and Data
313
External Memory Timing
315
External Memory Read
316
External Memory Write
319
External Memory Write
320
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle
322
Access Write Cycle
324
SCSI Timing Diagrams
336
Initiator Asynchronous Send
336
Initiator Asynchronous Receive
337
Target Asynchronous Send
337
Target Asynchronous Receive
338
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 40 Mhz Clock
339
Initiator and Target ST Synchronous Transfer
340
Initiator and Target DT Synchronous Transfer
340
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers or 20.0 Mbytes (16-Bit Transfers) 40 Mhz Clock
341
Mbyte (16-Bit Transfers) Quadrupled 40 Mhz Clock
342
Package Drawings
345
LSI53C1000 329 BGA Chip - Top View
346
Alphanumeric List by Signal Names
348
Alphanumeric List by BGA Positions
349
LSI53C1000 329 Ball Grid Array (Bottom View)
350
LSI53C1000 329 BGA Mechanical Drawing
351
Appendix A Register Summary
353
A.1 LSI53C1000 PCI Register Map
353
A.2 LSI53C1000 SCSI Register Map
355
Appendix B External Memory Interface Diagram Examples
361
Kbyte Interface with 200 Ns Memory
361
Kbyte Interface with 150 Ns Memory
362
Kbyte or 1 Mbyte Interface with 150 Ns Memory
363
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 Ns Memory
363
Kbyte Interface with 150 Ns Memory
364
Customer Feedback
377
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