I/O Processor; System Interface; Integrated 2 Gbaud Transceivers; Link Controllers - LSI LSIFC929 Technical Manual

Dual channel fibre channerl i/o processor

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1.3.3 I/O Processor

1-8

general purpose memory expansion bus supports up to 1 Mbyte of Flash

ROM.

The LSIFC929 uses a 32-bit ARM RISC processor to control all system

interface and message transport functionality. This frees the host CPU

for other processing activity and improves overall I/O performance. The

RISC processor and associated ﬁrmware have the ability to manage an

I/O from start to ﬁnish without host intervention. The RISC processor also

manages the message passing interface.

The system interface efﬁciently passes messages between the

LSIFC929 and other I/O agents. It consists of four hardware FIFOs for

the message queuing lists: Request Free, Request Post, Reply Free, and

Reply Post. Control logic for the FIFOs is provided within the LSIFC929

system interface with messages stored in external memory.

The LSIFC929 implements LSI Logic's GigaBlaze

transceivers. GigaBlaze is backward compatible with 1Gbaud systems,

using a ﬁrmware-implemented "Simple Autospeed Negotiation Algorithm"

for easy updates. The integrated 2 Gbaud transceivers provide a FC

compliant physical interface for cost conscious and real estate limited

applications.

The integrated link controller is FC-AL-2 (Rev. 7.0) compatible and

performs all link operations. The controller monitors the Link State and

strictly adheres to the Loop Port State Machine ensuring maximum

system interoperability. The link control interfaces to the integrated

transceiver.

Introduction

2 Gbaud integrated

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