Chapter 6
Appendix A
Appendix B
Appendix C
Figures
6.1
6.2
6.2.1
PCI Interface Timing Diagrams
6.2.2
Fibre Channel Interface Timings
6.2.3
6.3
6.4
6.5
Index
1.1
LSIFC929 Typical Implementation
1.2
2.1
2.2
2.3
2.4
2.5
2.6
Write Event Trellis
2.7
2.8
2.9
3.1
3.2
LSIFC929 Message Flow
Contents
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
6-1
6-6
6-6
6-18
6-19
6-22
6-26
6-27
1-5
1-7
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-8
2-9
3-2
3-5
xi