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3.1 Introduction
Chapter 3
LSIFC929 Overview
This chapter provides a general description of the LSIFC929 Fibre
Channel PCI Protocol Controller firmware. The chapter contains the
following sections:
•
Section 3.1, "Introduction"
•
Section 3.2, "Message Interface"
•
Section 3.3, "SCSI Message Class"
•
Section 3.4, "LAN Message Class"
•
Section 3.5, "Target Message Class"
•
Section 3.6, "Support Components"
The LSI Logic LSIFC929 is used to connect a host to a high speed FC
Link. The FCP ANSI standard, FC Private Loop Direct Attach, and Fabric
Loop Attach profiles are supported with the use of a sophisticated
firmware implementation. All profiles, specifications, and interoperability
maintained by the LSIFC929 are listed in
Specifications".
Although optimized for a 64-bit PCI interface to communicate with the
system CPU(s) and memory, the LSIFC929 also supports a 32-bit PCI
environment. The system interface to the LSIFC929 is designed to
minimize the amount of PCI bandwidth required to support I/O requests.
A packetized message passing interface is used to reduce the number
of single cycle PCI bus cycles. All FC Data traffic on the PCI bus occurs
with zero wait state bursts across the PCI bus.
The intelligent LSIFC929 architecture allows the system to specify I/Os
at the command level. The LSIFC929 manages I/Os at the Frame,
LSIFC929 Dual Channel Fibre Channel I/O Processor
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Appendix B, "Reference
3-1
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