LSI LSIFC929 Technical Manual page 7

Dual channel fibre channerl i/o processor
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Revision Record
Revision
Date
0.3
04/2000
1.0
05/2001
2.0
07/2001
Remarks
First Advance Information printing.
First Preliminary release.
Changes:
Converted the Manual to LSI format.
Table 4.2 - RTRIM description changed.
Table 4.2 - RXLOS0 and RXLOS1 descriptions changed.
Table 4.4 - Test Modes removed from MODE[7:0] description.
Section 5.3.2 - Note reworded.
Register 0x00C, page 5-14 - Cache Line Size description modified.
Register 0x040, page 5-31 - Changed this register from Read/Write to Write
Only.
Table 6.8 - Min/Max values and test conditions changed.
Figure 4.1 and Tables 4.1 and 4.2 have been moved to the end of Chapter
6, making the layout of this Manual consistent with our current guidelines.
They are now Figure 6.16 and Tables 6.16 and 6.17
Table 4.1 - new signals are added to the device, incorporating hot swap
capabilities. They are also added to Figure 6.16 and Tables 6.16 and 6.17.
Release of Final Manual.
Changes:
Deleted Section 1.7.
Removed "Draft" references from Manual.
Table 6.1 - Changed ESD maximum spec to 1.5 kV.
Section 6.2.2 - Referred user to the Fibre Channel Physical Interfaces
specification (FC-PI, Rev. 11) for Fibre Channel Interface Timings.
Appendix B, Table 6.8 - Updated the list of Reference Specifications.
Preface
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
vii

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